Xilinx LogiCORE 1000BASE-X User Manual page 58

R
be included in the frame supplied to the core. The RocketIO transceiver will replace these
four bytes with the calculated CRC value.
GMII Reception
The timing of normal inbound frame transfer with RocketIO transceiver CRC functionality
is illustrated in
received frame and checks it against that contained in the frames FCS field. The RocketIO
transceiver will assert RXCHECKINGCRC and RXCRCERR signals, as defined in the Virtex-II
Pro RocketIO Transceiver User Guide.
FCS field since RXCRCERR is not asserted.
Please note that RXCHECKINGCRC and RXCRCERR are obtained directly from the output of
the RocketIO transceiver. The core receiver behavior is unchanged.
58
gmii_txd[7:0]
gmii_tx_en
gmii_tx_er
Figure 5-8: GMII Frame Transmission with RocketIO Transceiver CRC Logic
Figure 5-9. The RocketIO transceiver calculates the CRC value of the
preamble
gmii_rxd[7:0]
gmii_rx_dv
gmii_rx_er
RXCHECKINGCRC
RXCRCERR
Figure 5-9: GMII Frame Reception with the RocketIO Transceiver CRC Logic
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Chapter 5: Using the Client-side GMII Data Path
preamble
Enabled
Figure 5-9 illustrates a frame received with a correct
Enabled
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
4 place holder bytes
FCS
3 clock periods
UG155 March 24, 2008