Client Side Interface - Xilinx LogiCORE 1000BASE-X User Manual

Core Interfaces
Figure 2-7
the optional dynamic switching logic (between 1000BASE-X and SGMII standards). This
mode is shown used with a RocketIO transceiver interface. For more information, see
Chapter 11, "Dynamic Switching of 1000BASE-X and SGMII Standards."

Client Side Interface

GMII Pinout
Table 2-1
parameterizations of the core. These are typically attached to an Ethernet MAC, either off-
chip or internally integrated. The HDL example design delivered with the core connects
these signals to IOBs to provide a place-and-route example.
For more information, see
Standard" in Chapter
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
shows the pinout for the Ethernet 1000BASE-X PCS/PMA or SGMII core using
GMII gmii_txd[7:0]
gmii_tx_en
gmii_tx_er
gmii_rxd[7:0]
gmii_rx_dv
gmii_rx_er
gmii_isolate
MDIO
mdc
mdio_in
mdio_out
mdio_tri
phyad[4:0]
reset
gtx_clk
Auto_Negotiation
an_interrupt
link_timer_basex[8:0]
link_timer_sgmii[8:0]
basex_or_sgmii
Figure 2-7: Component Pinout with the Dynamic Switching Logic
describes the GMII-side interface signals of the core common to all
"Designing with the Client-side GMII for the 1000BASE-X
5.
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RocketIO Interface
mgt_rx_reset
mgt_tx_reset
userclk
userclk2
dcm_locked
rxbufstatus[1:0]
rxchariscomma
rxcharisk
rxclkcorcnt[2:0]
rxdata[7:0]
rxdisperr
rxnotintable
rxrundisp
txbuferr
powerdown
txchardispmode
txchardispval
txcharisk
txdata
enablealign
signal_detect
status_vector[4:0]
R
31