Xilinx LogiCORE 1000BASE-X User Manual
  1. Manuals
  2. Brands
  3. Xilinx Manuals
  4. Software
  5. LogiCORE 1000BASE-X
  6. User manual
Xilinx LogiCORE 1000BASE-X User Manual

Xilinx LogiCORE 1000BASE-X User Manual

Logicore ip ethernet 1000base-x pcs/pma or sgmii v9.1
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
LogiCORE™ IP
Ethernet 1000BASE-X
PCS/PMA or SGMII v9.1
User Guide
UG155 March 24, 2008
R

Advertisement

Table of Contents
loading

Related Manuals for Xilinx LogiCORE 1000BASE-X

Summary of Contents for Xilinx LogiCORE 1000BASE-X

  • Page 1 LogiCORE™ IP Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 User Guide UG155 March 24, 2008...

  • Page 2: Revision History

    Specification. Xilinx reserves the right to make changes, at any time, to the Specification as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Specification.

  • Page 3: Table Of Contents

    ............21 Related Xilinx Ethernet Products and Services ....... . 22 Specifications .
  • Page 4 Virtex-4 FX Devices ............109 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1...
  • Page 5 Switching Constraints ..........167 Virtex-5 RocketIO GTX Transceivers for 1000BASE-X Constraints ....167 Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 6 Generating the Xilinx Netlist ........
  • Page 7 Debugging ............. . 229 Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 8 Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 9: Schedule Of Figures

    Figure 5-18: External GMII Receiver Logic ..........67 Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 10 Figure 10-2: SGMII Auto-Negotiation ........... 155 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1...
  • Page 11 Figure E-3: TBI Elastic Buffer Size for All Families........223 Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 12 Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 13: Schedule Of Tables

    Table 9-20: SGMII Status (Register 1)......... . . 137 Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 14 Capabilities of the Rx Elastic Buffers ........226 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1...

  • Page 15: Preface: About This Guide

    About This Guide The LogiCORE™ IP Ethernet 1000BASE-X PCS/PMA or SGMII User Guide provides information about generating a Xilinx Ethernet 1000BASE-X PCS/PMA or SGMII core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools.

  • Page 16: Conventions

    Emphasis in text overlaps the pin of a symbol, the two nets are not connected. Items that are not supported Dark Shading This feature is not supported or reserved www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 17: Online Document

    Blue text location in the current “Title Formats” in document Chapter 1 for details. Go to www.xilinx.com for the Blue, underlined text Hyperlink to a website (URL) latest speed files. Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 18 Preface: About This Guide www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 19: Chapter 1: Introduction

    About the Core The Ethernet 1000BASE-X PCS/PMA or SGMII core is a Xilinx CORE Generator™ IP core, included in the latest IP Update on the Xilinx IP Center. For detailed information about the core, see the Ethernet 100BASE-X PCS/PMA product page.

  • Page 20: Additional Core Resources

    Questions are routed to a team of engineers with expertise using the Ethernet 1000BASE-X PCS/PMA or SGMII core. Xilinx provides technical support for use of this product as described in the Ethernet 1000BASE-X PCS/PMA or SGMII User Guide and the Ethernet 1000BASE-X PCS/PMA or SGMII Getting Started Guide.

  • Page 21: Document

    Feedback Document For comments or suggestions about this document, please submit a WebCase from www.support.xilinx.com/. Be sure to include the following information: • Document title • Document number • Page number(s) to which your comments refer • Explanation of your comments Ethernet 1000BASE-X PCS/PMA or SGMII v9.1...
  • Page 22 Chapter 1: Introduction www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 23: Chapter 2: Core Architecture

    8B/10B encoding/decoding, the PMA SERDES, and clock recovery. Figure 2-1 illustrates the remaining PCS sublayer functionality, and also shows the major functional blocks of the core. Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 24 (link partner), and to detect corresponding operational modes that the link partner may be advertising. Auto-Negotiation is controlled and monitored through the PCS Management Registers. Chapter 10, “Auto-Negotiation.” www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 25: Ethernet 1000Base-X Pcs/Pma Or Sgmii With Ten-Bit-Interface

    These are shown in the surrounded by the dotted line box in Figure 2-2 are described in the following sections. The other blocks are described previously in this document. Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 26: Core Interfaces

    IBUFs, OBUFs, and IOB flip-flops to the external signals of the GMII and TBI. IOBs are added to the remaining unconnected ports to take the example design through the Xilinx implementation software. All clock management logic is placed in this example design, allowing you more flexibility in implementation (such as designs using multiple cores).
  • Page 27 Auto_Negotiation an_interrupt link_timer_value[8:0] signal_detect status_vector[4:0] Figure 2-3: Component Pinout Using RocketIO Transceiver with PCS Management Registers Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 28 MDIO Replacement rxnotintable rxrundisp txbuferr configuration_vector[3:0] powerdown txchardispmode txchardispval reset txcharisk gtx_clk txdata enablealign signal_detect status_vector[4:0] Figure 2-4: Component Pinout Using RocketIO Transceiver without PCS Management Registers www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 29 MDIO rx_code_group1[9:0] mdio_in pma_rx_clk0 mdio_out pma_rx_clk1 mdio_tri phyad[4:0] reset gtx_clk signal_detect status_vector[4:0] Auto_Negotiation an_interrupt link_timer_value[8:0] Figure 2-5: Component Pinout Using the Ten-Bit Interface with PCS Management Registers Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 30 MDIO Replacement rx_code_group1[9:0] pma_rx_clk0 pma_rx_clk1 configuration_vector[3:0] reset gtx_clk signal_detect status_vector[4:0] Figure 2-6: Component Pinout Using Ten-Bit Interface without PCS Management Registers www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 31: Client Side Interface

    The HDL example design delivered with the core connects these signals to IOBs to provide a place-and-route example. For more information, see “Designing with the Client-side GMII for the 1000BASE-X Standard” in Chapter Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 32 2. These signals are synchronous to the core’s internal 125 MHz reference clock. This is userclk2 when the core is used with the RocketIO transceiver; gtx_clk when the core is used with TBI. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1...
  • Page 33 1. These signals are synchronous to the core’s internal 125 MHz reference clock. This is userclk2 when the core is used with the RocketIO transceiver; this is gtx_clk when the core is used with TBI. Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 34 1. These signals can be connected to a Tri-state buffer to create a bidirectional mdio signal suitable for connection to an external MDIO controller (for example, an Ethernet MAC). www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 35 1. These signals are synchronous to the core’s internal 125 MHz reference clock. This is userclk2 when the core is used with the RocketIO transceiver; this is gtx_clk when the core is used with TBI. Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 36: Physical Side Interface

    RocketIO transceiver in the appropriate HDL example design delivered with the core. For more information, see: • Chapter 7, “1000BASE-X with RocketIO Transceivers” • Chapter 8, “SGMII / Dynamic Standards Switching with RocketIO Transceivers” www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 37 Connects to ENMCOMMAALIGN and ENPCOMMAALIGN of the RocketIO. 1. When the core is used with a RocketIO transceiver, userclk2 is used as the 125 MHz reference clock for the entire core. Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 38 180 degrees out of phase with pma_rx_clk0. en_cdet Output gtx_clk Enables the PMA Sublayer to perform comma realignment. This is driven from the PCS Receive Engine during the Loss-Of-Sync state. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 39: Chapter 3: Generating And Customizing The Core

    Ethernet 1000BASE-X PCS/PMA or SGMII customization screen, used to set core parameters and options. For help starting and using CORE Generator on your system, see the documentation included with ISE™, including the CORE Generator Guide, at www.xilinx.com/support/software_manuals.htm. Figure 3-1: Core Customization Screen Component Name The component name is used as the base name of the output files generated for the core.

  • Page 40: Select Standard

    MDIO Management Interface. For more information, see Chapter 9, “Configuration and Status.” Core Functionality Figure 3-2 displays the Ethernet 1000BASE-X PCS/PMA or SGMII functionality screen. Figure 3-2: 1000BASE-X Standard Options Screen www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 41: Sgmii/Dynamic Standard Switching Elastic Buffer Options

    1000BASE-X PCS/PMA or SGMII core, is only displayed if either SGMII or Both is selected in the Select Standard section of the initial customization screen, and only if RocketIO is selected as the Physical Standard. Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 42 Figure 3-3: SGMII/Dynamic Standard Switching Options Screen This screen lets you select the Receiver Elastic Buffer type to be used with the core. Before selecting this option, see “Receiver Elastic Buffer Implementations” in Chapter www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 43: Rocketio Tile Configuration

    GUI, except that underscore characters (_) may be used instead of spaces. The text in an XCO file is not case sensitive. Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 44: Output Generation

    See the Ethernet 1000BASE-X PCS/PMA or SGMII Getting Started Guide for a complete description of the CORE Generator output files, simulation requirements, and detailed information about the HDL example design. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 45: Chapter 4: Designing With The Core

    1000BASE-X PCS/PMA or SGMII core. Design guidelines, as well as the variety of implementations presented, are based on the example design delivered with the core. See the Xilinx Ethernet 1000BASE-X PCS/PMA or SGMII Getting Started Guide for information about the example design delivered with the core.
  • Page 46 IOBs Elastic Buffer Ethernet Connect to (Connect to 1000BASE-X RocketIO Client MA Optical PCS/PMA Transceiver ansceiver) Core IOBs Clock Management Logic Figure 4-1: 1000BASE-X Standard Using a RocketIO Transceiver www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 47 IOBs Elastic IOBs Buffer Ethernet Connect to 1000BASE-X (Connect to Client MAC PCS/PMA SERDES) Core IOBs IOBs (DDR) Clock Management Logic Figure 4-2: Example Design 1000BASE-X Standard Using TBI Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 48 Ethernet SGMII GMII-style Serial GMII 1000BASE-X Adaptation 8-bit I/F (SGMII) PCS/PMA RocketIO Module Core Fabric IOBs Elastic Buffer Clock Management Logic Figure 4-3: Example Design Performing the SGMII Standard www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 49 IOBs IOBs Ethernet SGMII GMII-style 1000BASE-X (Connect to Adaptation 8-bit I/F PCS/PMA SERDES) Module Core IOBs IOBs (DDR) Clock Management Logic Figure 4-4: Example Design Performing the SGMII Standard Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 50: Design Guidelines

    Run the implement script in the /implement directory to create a top-level netlist for the design. The script may also run the Xilinx tools map, par, and bitgen to create a bitstream that can be downloaded to a Xilinx device. SimPrim-based simulation models for the entire design are also produced by the implement scripts.
  • Page 51 Create a Bitstream Run the Xilinx tools map, par, and bitgen to create a bitstream that can be downloaded to a Xilinx device. The UCF produced by the CORE Generator should be used as the basis for the user UCF and care must be taken to constrain the design correctly.
  • Page 52 While registering signals may not be possible for all paths, it simplifies timing analysis and makes it easier for the Xilinx tools to place and route the design. Recognize Timing Critical Signals The UCF provided with the example design for the core identifies the critical signals and the timing constraints that should be applied.

  • Page 53: Chapter 5: Using The Client-Side Gmii Data Path

    Figure 5-1: GMII Normal Frame Transmission Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 54: Gmii Reception

    Frame Delimiter (SFD) to be lost in the network. The SFD will always be present in well- formed frames. gmii_rxd[7:0] preamble gmii_rx_dv gmii_rx_er Figure 5-3: GMII Normal Frame Reception www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 55 0x1F, also illustrated in Figure 5-5. gmii_rxd[7:0] preamble 0x0F 0x0F 0x1F gmii_rx_dv gmii_rx_er error during frame error during extension Figure 5-5: GMII Frame Reception with Errors Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 56: Status_Vector[4:0] Signals

    This signal indicates the state of the synchronization state machine (IEEE802.3 figure 36-9). This signal is similar to Bit[0] (Link Status), but is NOT qualified with Auto-Negotiation. When high, link synchronization has been obtained. When low, synchronization has failed. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 57: Using The Virtex-Ii Pro Rocketio Transceiver Crc Functionality

    5-8. This figure shows that an Ethernet frame can be completed by allowing the RocketIO transceiver to create the Frame Check Sequence field (FCS) using the in-built CRC logic. For this to be successful, four place-holder bytes must Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 58 RocketIO transceiver. The core receiver behavior is unchanged. preamble gmii_rxd[7:0] gmii_rx_dv gmii_rx_er RXCHECKINGCRC RXCRCERR 3 clock periods Figure 5-9: GMII Frame Reception with the RocketIO Transceiver CRC Logic Enabled www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 59: Designing With Client-Side Gmii For The Sgmii Standard

    10 clock periods Figure 5-11: GMII Data Transmission at 100 Mbps Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 60: Gmii Reception

    Ethernet MAC, to sample this data correctly. userclk2 gmii_rxd[7:0] preamble gmii_rx_dv gmii_rx_er 10 clock periods Figure 5-13: GMII Data Reception at 100 Mbps www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 61: Using The Gmii As An Internal Connection

    Elastic Buffer is provided for the 1000BASE-X standard by the example design provided with the core. See the Ethernet 1000BASE-X PCS/PMA or SGMII Getting Started Guide for more information. Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 62 (if TBI is used) Transmitter Elastic Buffer IBUF gmii_txd[0] gmii_txd_ibuf[0] gmii_txd_int[0] gmii_txd[0] IPAD IBUF gmii_tx_en gmii_tx_en_ibuf gmii_tx_en_int gmii_tx_en IPAD IBUF gmii_tx_er gmii_tx_er_int gmii_tx_er_ibuf gmii_tx_er IPAD Figure 5-14: GMII Transmitter Logic www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 63 IPAD IBUF gmii_tx_en gmii_tx_en_ibuf gmii_tx_en_int gmii_tx_en IPAD IBUF gmii_tx_er gmii_tx_er_int gmii_tx_er_ibuf gmii_tx_er IPAD Figure 5-15: External GMII Transmitter Logic for Spartan-3, Spartan-3E and Spartan-3A Devices Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 64 Elastic Buffer IBUF gmii_txd[0] gmii_txd_int[0] IDELAY gmii_txd[0] IPAD IBUF gmii_tx_en gmii_tx_en_int IDELAY gmii_tx_en IPAD IBUF gmii_tx_er gmii_tx_er_int gmii_tx_er IDELAY IPAD Figure 5-16: External GMII Transmitter Logic for Virtex-4 Devices www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 65 Elastic Buffer IBUF gmii_txd[0] gmii_txd_int[0] IODELAY gmii_txd[0] IPAD IBUF gmii_tx_en gmii_tx_en_int IODELAY gmii_tx_en IPAD IBUF gmii_tx_er gmii_tx_er_int gmii_tx_er IODELAY IPAD Figure 5-17: External GMII Transmitter Logic for Virtex-5 Devices Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 66: Gmii Receiver Logic

    The clock name varies depending on the CORE Generator options. When used with the RocketIO transceiver, the clock name is userclk2; when used with the TBI, the clock name is gtx_clk. For more information on clocking, see Chapters 6, 7 and 8. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 67 OBUFT Ethernet 1000BASE-X PCS/PMA or SGMII LogiCORE gmii_isolate gmii_rxd[0] gmii_rxd_obuf[0] gmii_rxd[0] OPAD OBUFT gmii_rx_dv gmii_rx_dv_obuf gmii_rx_dv OPAD OBUFT gmii_rx_er gmii_rx_er_obuf gmii_rx_er OPAD OBUFT Figure 5-18: External GMII Receiver Logic Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 68 Chapter 5: Using the Client-side GMII Data Path www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 69: Chapter 6: The Ten-Bit Interface

    Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 70: Receiver Logic

    (pma_rx_clk0 and pma_rx_clk1 are 180 degrees out of phase with each other). This splits the input TBI data bus, rx_code_group[9:0], up into two buses: rx_code_group0_reg[9:0] and rx_code_group1_reg[9:0], www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 71: Figure 6-2: Ten-Bit-Interface Receiver Logic

    IPAD IOB LOGIC BUFG IBUFG pma_rx_clk1_bufg pma_rx_clk1 (62.5 MHz) pma_rx_clk1_ibufg pma_rx_clk1 IPAD IOB LOGIC IBUF rx_code_group[0] rx_code_group0_reg[0] rx_code_group0[0] IPAD rx_code_group1_reg[0] rx_code_group1[0] rx_code_group_ibuf[0] Figure 6-2: Ten-Bit-Interface Receiver Logic Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 72 CLKIN CLK0 IPAD pma_rx_clk1_bufg (62.5 MHz) IOB LOGIC IBUF rx_code_group[0] rx_code_group0_reg[0] rx_code_group0[0] IPAD rx_code_group1_reg[0] rx_code_group1[0] rx_code_group_ibuf[0] Figure 6-3: TBI Receiver Logic for Spartan-3, Spartan-3E, and Spartan-3A Devices www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 73 BUFG IBUFG pma_rx_clk0 pma_rx_clk0 IDELAY IPAD pma_rx_clk1 IOB LOGIC IDDR rx_code_group0_reg[0] rx_code_group0[0] IBUF IDELAY IPAD rx_code_group1_reg[0] rx_code_group1[0] rx_code_group[0] Figure 6-4: Ten-Bit Interface Receiver Logic - Virtex-4 Device (Example Design) Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 74 IOB LOGIC BUFG IBUFG pma_rx_clk1 rx_code_group[0] IDELAY pma_rx_clk1 IPAD pma_rx_clk1_bufg (62.5 MHz) IOB LOGIC IBUF rx_code_group[0] rx_code_group1_reg[0] rx_code_group1[0] IDELAY IPAD Figure 6-5: Alternate Ten-Bit Interface Receiver Logic for Virtex-4 Devices www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 75 BUFG IBUFG pma_rx_clk0 pma_rx_clk0 IODELAY IPAD pma_rx_clk1 IOB LOGIC IDDR rx_code_group0_reg[0] rx_code_group0[0] IBUF IODELAY IPAD rx_code_group1_reg[0] rx_code_group1[0] rx_code_group[0] Figure 6-6: Ten-Bit Interface Receiver Logic - Virtex-5 Device (Example Design) Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 76 IOB LOGIC BUFG IBUFG pma_rx_clk1 rx_code_group[0] pma_rx_clk1 IODELAY IPAD pma_rx_clk1_bufg (62.5 MHz) IOB LOGIC IBUF rx_code_group[0] rx_code_group1_reg[0] rx_code_group1[0] IODELAY IPAD Figure 6-7: Alternate Ten-Bit Interface Receiver Logic - Virtex-5 Devices www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 77: Clock Sharing Across Multiple Cores With Tbi

    Block Level Ethernet 1000BASE-X PCS/PMA or SGMII Core BUFG IBUFG pma_rx_clk0#2 pma_rx_clk0 gtx_clk BUFG IBUFG pma_rx_clk1#2 pma_rx_clk1 Figure 6-8: Clock Management, Multiple Core Instances with Ten-Bit Interface Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 78 Chapter 6: The Ten-Bit Interface www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 79: Chapter 7: 1000Base-X With Rocketio Transceivers

    7-1). For detailed information, see “Virtex-II Pro RocketIO MGTs for 1000BASE-X Constraints,” and the RocketIO Transceiver User Guide. Note: The brefclk differential pair applied to the MGT is of frequency 62.5 MHz. Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 80: Figure 7-1: 1000Base-X Connection To A Virtex-Ii Pro Mgt

    RXDISPERR LOOPBACK[1:0] powerdown POWERDOWN txchardispmode TXCHARDISPMODE txchardispval TXCHARDISPVAL txcharisk TXCHARISK txdata[7:0] TXDATA[7:0] enablealign ENPCOMMAALIGN ENMCOMMAALIGN RXRECCLK RXPOLARITY TXPOLARITY TXFORCECRCERR TXINHIBIT Figure 7-1: 1000BASE-X Connection to a Virtex-II Pro MGT www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 81: Virtex-4 Fx Devices

    Calibration blocks require a clock source of between 25 to 50 MHz that is shared with the Dynamic Reconfiguration Port (DRP) of the MGT, which is named dclk in the example design. See Xilinx Answer Record 22477 for more information.

  • Page 82: Figure 7-2: 1000Base-X Connection To Virtex-4 Mgt

    POWERDOWN txchardispmode TXCHARDISPMODE txchardispval TXCHARDISPVAL txcharisk TXCHARISK txdata[7:0] TXDATA[7:0] enablealign ENPCOMMAALIGN ENMCOMMAALIGN BUFG dclk DCLK Cal Block v1.4.1 DCLK signal_detect RX_SIGNAL_DETECT TX_SIGNAL_DETECT Figure 7-2: 1000BASE-X Connection to Virtex-4 MGT www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 83: Virtex-5 Lxt And Sxt Devices

    The XCO file itself contains a list of all of the GTP Wizard attributes which were used. For further information, please refer to the Virtex-5 RocketIO GTP Wizard Getting Started Guide (UG188) and the CORE Generator Guide, at www.xilinx.com/support/software_manuals.htm Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com...

  • Page 84: Figure 7-3: 1000Base-X Connection To Virtex-5 Gtp Transceivers

    RXDISPERR0 SHIM rxdata[7:0] RXDATA[07:0] rxrundisp RXRUNDISP0 RXCLKCORCNT[2:0] rxclkcorcnt[2:0] powerdown POWERDOWN0 txchardispmode TXCHARDISPMODE0 txchardispval TXCHARDISPVAL0 txcharisk TXCHARISK0 txdata[7:0] TXDATA[07:0] enablealign RXENMCOMMAALIGN0 RXENPCOMMAALIGN0 Figure 7-3: 1000BASE-X Connection to Virtex-5 GTP Transceivers www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 85: Virtex-5 Fxt Devices

    The XCO file itself contains a list of all of the GTX Wizard attributes which were used. For further information, please refer to the Virtex-5 RocketIO GTX Wizard Getting Started Guide and the CORE Generator Guide, at www.xilinx.com/support/software_manuals.htm Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com...
  • Page 86 RXDISPERR0 SHIM rxdata[7:0] RXDATA[07:0] rxrundisp RXRUNDISP0 RXCLKCORCNT[2:0] rxclkcorcnt[2:0] powerdown POWERDOWN0 txchardispmode TXCHARDISPMODE0 txchardispval TXCHARDISPVAL0 txcharisk TXCHARISK0 txdata[7:0] TXDATA[07:0] enablealign RXENMCOMMAALIGN0 RXENPCOMMAALIGN0 Figure 7-4: 1000BASE-X Connection to Virtex-5 GTX Transceivers www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 87: Clock Sharing Across Multiple Cores With Rocketio

    _block (Block Level) Ethernet 1000BASE-X GT_ETHERNET_1 PCS/PMA or SGMII core BREFCLK userclk TXUSRCLK userclk2 TXUSRCLK2 RXUSRCLK RXUSRCLK2 Figure 7-5: Clock Management: Two Core Instances, Virtex-II Pro MGTs for 1000BASE-X Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 88: Virtex-4 Fx Devices

    MGTs in the column. Although not illustrated in Figure 7-6, dclk (the clock used for the calibration blocks and for the Dynamic Reconfiguration Port (DRP) of the MGTs) can also be shared. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 89: Figure 7-6: Clock Management - Multiple Core Instances, Mgts For 1000Base-X

    RXUSRCLK2 PCS/PMA or SGMII core Virtex-4 GT11 RocketIO userclk userclk2 TXOUTCLK1 REFCLK1 TXUSRCLK ‘0’ TXUSRCLK2 RXUSRCLK ‘0’ RXUSRCLK2 Figure 7-6: Clock Management - Multiple Core Instances, MGTs for 1000BASE-X Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 90: Virtex-5 Lxt And Sxt Devices

    To provide the 125 MHz clock for all core instances, select a REFCLKOUT port from any GTP transceiver. This can be routed onto global clock routing using a BUFG as illustrated and shared between all cores and GTP transceivers. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 91: Figure 7-7: Clock Management - Multiple Core Instances, Virtex-5 Rocketio Gtp

    Ethernet 1000BASE-X RXUSRCLK20 PCS/PMA or SGMII core CLKIN Virtex-5 RocketIO userclk userclk2 TXUSRCLK1 TXUSRCLK21 RXUSRCLK1 RXUSRCLK21 Figure 7-7: Clock Management - Multiple Core Instances, Virtex-5 RocketIO GTP Transceivers for 1000BASE-X Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 92: Virtex-5 Fxt Devices

    GTX transceiver and route this to a single DCM. The CLK0 (125MHz) and CLKDV (62.5MHz) outputs from this DCM, placed onto global clock routing using a BUFGs, can be shared across all core instances and GTX transceivers as illustrated. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 93: Transceivers

    Ethernet 1000BASE-X RXUSRCLK20 PCS/PMA or SGMII core CLKIN Virtex-5 RocketIO userclk userclk2 TXUSRCLK1 TXUSRCLK21 RXUSRCLK1 RXUSRCLK21 Figure 7-8: Clock Management - Multiple Core Instances, Virtex-5 RocketIO GTX Transceivers for 1000BASE-X Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 94: Transceivers

    Chapter 7: 1000BASE-X with RocketIO Transceivers www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 95: Chapter 8: Sgmii / Dynamic Standards Switching With Rocketio Transceivers

    The second option, 10/100/1000 Mbps (restricted tolerance for clocks) or 100/1000 Mbps, uses the receiver elastic buffer present in the RocketIOs. This is half the size and can potentially underflow or overflow during SGMII frame reception at 10 Mbps operation Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 96: The Requirement For The Fpga Fabric Rx Elastic Buffer

    At 100 Mbps operation, this translates into 15220 clock cycles (as each byte is repeated 10 times). • At 10 Mbps operation, this translates into 152200 clock cycles (as each byte is repeated 100 times). www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 97: The Rocketio Rx Elastic Buffer

    • 10 Mbps operation is not required (for example, when connecting the core to the Xilinx 1-Gigabit Ethernet MAC to provide only 1 Gbps operation). Both 1 Gbps and 100 Mbps operation can be guaranteed. • When the clocks are closely related (see the following section).

  • Page 98: Rocketio Logic Using The Rocketio Rx Elastic Buffer

    RocketIO as well as all clock circuitry in the system are identical to the 1000BASE-X implementation. For a detailed explanation, see Chapter 7, “1000BASE-X with RocketIO Transceivers.” www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 99: Virtex-Ii Pro Devices

    “Virtex-II Pro RocketIO MGTs for SGMII or Dynamic Standards Switching Constraints,” page 163 for constraint details. This methodology is also described in XAPP763. Note: The brefclk differential pair applied to the MGT is of frequency 62.5 MHz. Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 100: Figure 8-3: Sgmii Connection To A Virtex-Ii Pro Rocketio Transceiver

    Elastic Buffer RXDATA[15:0] rxdata[7:0] RXDISPERR[1:0] rxdisperr RXUSRCLK RXUSRCLK2 ENPCOMMAALIGN enablealign ENMCOMMAALIGN RXRECCLK local RXPOLARITY clock TXPOLARITY routing TXFORCECRCERR TXINHIBIT Figure 8-3: SGMII Connection to a Virtex-II Pro RocketIO Transceiver www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 101: Virtex-4 Devices For Sgmii Or Dynamic Standards Switching

    Calibration blocks require a clock source of between 25 to 50 MHz, which is shared with the Dynamic Reconfiguration Port (DRP) of the MGT, named dclk in the example design. See Xilinx Answer Record 22477 for more information.

  • Page 102: Figure 8-4: Sgmii Connection To A Virtex-4 Mgt

    TXCHARDISPMODE txchardispval TXCHARDISPVAL txcharisk TXCHARISK txdata[7:0] TXDATA[7:0] enablealign ENPCOMMAALIGN BUFG ENMCOMMAALIGN dclk DCLK Cal Block v1.4.1 DCLK signal_detect RX_SIGNAL_DETECT TX_SIGNAL_DETECT Figure 8-4: SGMII Connection to a Virtex-4 MGT www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 103: Virtex-5 Lxt Or Sxt Devices For Sgmii Or Dynamic Standards Switching

    The XCO file itself contains a list of all of the GTP Wizard attributes which were used. For further information, please refer to the Virtex-5 RocketIO GTP Wizard Getting Started Guide (UG188) and the CORE Generator Guide, at www.xilinx.com/support/software_manuals.htm Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com...

  • Page 104: Figure 8-5: Sgmii Connection To A Virtex-5 Rocketio Gtp Transceiver

    RXDISPERR0 RXUSRCLK0 RXUSRCLK20 BUFR RXRECCLK0 powerdown POWERDOWN0 txchardispmode TXCHARDISPMODE0 txchardispval TXCHARDISPVAL0 txcharisk TXCHARISK0 txdata[7:0] TXDATA[07:0] RXENPCOMMAALIGN0 enablealign RXENMCOMMAALIGN0 Figure 8-5: SGMII Connection to a Virtex-5 RocketIO GTP Transceiver www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 105: Virtex-5 Fxt Devices For Sgmii Or Dynamic Standards Switching

    The XCO file itself contains a list of all of the GTX Wizard attributes which were used. For further information, please refer to the Virtex-5 RocketIO GTX Wizard Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 106: Figure 8-6: Sgmii Connection To A Virtex-5 Rocketio Gtx Transceiver

    Chapter 8: SGMII / Dynamic Standards Switching with RocketIO Transceivers Getting Started Guide and the CORE Generator Guide, at www.xilinx.com/support/software_manuals.htm BUFG userclk2 CLKIN CLK0 (125MHz) IBUFGDS brefclkp IPAD IPAD CLKDV clkin userclk (62.5MHz) brefclkn (125MHz) BUFG rocketio_wrapper_gtp component_name_block rocketio_wrapper_gtp_tile (Block Level from...

  • Page 107: Clock Sharing - Multiple Cores With Rocketio, Fabric Elastic Buffer

    When using the fixed routing resources of brefclk, MGTs along the top edge of the device must use a separate brefclk routing resource to those along the bottom edge of Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 108: Figure 8-7: Clock Management With Multiple Core Instances With Virtex-Ii Pro

    TXUSRCLK userclk TXUSRCLK2 userclk2 FPGA local fabric RXUSRCLK clock RXUSRCLK2 Elastic routing RXRECCLK Buffer Figure 8-7: Clock Management with Multiple Core Instances with Virtex-II Pro RocketIO Transceivers for SGMII www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 109: Virtex-4 Fx Devices

    8-8–these cannot be shared across multiple MGTs. Although not illustrated in Figure 8-8, dclk (the clock used for the calibration blocks and for the Dynamic Reconfiguration Port (DRP) of the MGTs) can also be shared. Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 110 TXOUTCLK1 REFCLK1 userclk TXUSRCLK ‘0’ userclk2 TXUSRCLK2 ‘0’ RXUSRCLK FPGA fabric RXUSRCLK2 Elastic RXRECCLK1 Buffer BUFR Figure 8-8: Clock Management with Multiple Core Instances with Virtex-4 MGTs for SGMII www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 111: Virtex-5 Lxt And Sxt Devices

    Each GTP and core pair instantiated has its own independent clock domains synchronous to RXRECCLK0 and RXRECCLK1. These are placed on regional clock routing using a BUFR, as illustrated in Figure 8-9, and cannot be shared across multiple GTP transceivers. Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 112: Figure 8-9: Clock Management With Multiple Core Instances With Virtex-5 Gtp

    SGMII core RocketIO userclk TXUSRCLK1 userclk2 TXUSRCLK21 RXUSRCLK1 FPGA fabric RXUSRCLK21 Elastic RXRECCLK1 Buffer BUFR Figure 8-9: Clock Management with Multiple Core Instances with Virtex-5 GTP RocketIO Transceivers for SGMII www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 113: Virtex-5 Fxt Devices

    Each GTX and core pair instantiated has its own independent clock domains synchronous to RXRECCLK0 and RXRECCLK1. These are placed on regional clock routing using a BUFR, as illustrated in Figure 8-9, and cannot be shared across multiple GTX transceivers. Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 114: Figure 8-10: Clock Management With Multiple Core Instances With Virtex-5 Gtx

    SGMII core RocketIO userclk TXUSRCLK1 userclk2 TXUSRCLK21 RXUSRCLK1 FPGA fabric RXUSRCLK21 Elastic RXRECCLK1 Buffer BUFR Figure 8-10: Clock Management with Multiple Core Instances with Virtex-5 GTX RocketIO Transceivers for SGMII www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 115: Chapter 9: Configuration And Status

    An Ethernet MAC is shown as the MDIO bus master (the Station Management (STA) entity). Two PHY devices are shown connected to the same bus, both of which are MDIO slaves (MDIO Managed Device (MMD) entities). Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 116: Mdio Transactions

    MDIO wire synchronously to MDC. The abbreviations are used in this section are explained in Table 9-1. Table 9-1: Abbreviations and Terms Abbreviation Term Preamble Start of frame Operation code www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 117: Mdio Addressing

    Figure 9-1, two PHY devices are attached to the MDIO bus. Each of these has a different physical address. To address the intended PHY, its physical address should be Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 118: Connecting The Mdio To An Internally Integrated Sta

    This Tri-State buffer can either be external to the FPGA, or internally integrated by using an IOB IOBUF component with an appropriate SelectIO™ standard suitable for the external PHY. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 119: Management Registers

    22 of the IEEE 802.3 specification. Registers at undefined addresses are read-only and return 0s. Table 9-2: MDIO Registers for 1000BASE-X with Auto-Negotiation Register Address Register Name Control Register Status Register Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 120 With the TBI version, Bit 1 is connected to ewrap. When set to ‘1,’ indicates to the external PMA module to enter loopback mode. “Loopback,” page 197. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 121 1000 Mbps is identified. Unidirectiona Enable transmit regardless of Read/ write l Enable whether a valid link has been established. 0.4:0 Reserved Always return 0s, writes ignored. Returns 0s 00000 Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 122 Always returns a ‘1’ to indicate that Returns 1 Suppression Management Frame Preamble Suppression is supported. Auto- Negotiation 1 = Auto-Negotiation process completed Read only Complete 0 = Auto-Negotiation process not completed www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 123 For more information, see the 802.3 specification. Registers 2 and 3: PHY Identifiers Registers 2 and 3: PHY Identifiers Reg 2 10 9 Reg 3 Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 124 4.8:7 Pause 00 = No PAUSE read/write 01 = Symmetric PAUSE 10 = Asymmetric PAUSE towards link partner 11 = Both Symmetric PAUSE and Asymmetric PAUSE towards link partner www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 125 0s 5.8:7 Pause 00 = No PAUSE read only 01 = Symmetric PAUSE 10 = Asymmetric PAUSE towards link partner 11 = Both Symmetric PAUSE and Asymmetric PAUSE supported Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 126 Reserved Always returns 0s returns 0s 0000000 Register 7: Next Page Transmit MDIO Register 7: Next Page Transmit 15 14 13 12 11 Reg 7 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 127 Used by Auto-Negotiation function read only to indicate reception of a link partner’s base or next page 8.13 Message Page 1 = Message Page read only 0 = Unformatted Page Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 128 15.12 1000BASE-T Always returns a ‘0’ for this bit since returns 0 Half Duplex 1000BASE-T Half Duplex is not supported 15:11:0 Reserved Always return 0s returns 0s 000000000000 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 129: 1000Base-X Standard Without The Optional Auto-Negotiation

    Registers at undefined addresses are read-only and return 0s. Table 9-13: MDIO Registers for 1000BASE-X without Auto-Negotiation Register Address Register Name Control Register Status Register PHY Identifier Extended Status Register Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 130 This bit requires a reset (see bit 0.15) to clear. With the TBI version this register bit has no effect. 0.10 Isolate 1 = Electrically Isolate PHY from GMII read/write 0 = Normal operation www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 131 0 Mbps Full Duplex is not supported 1.11 10 Mbps Half Duplex Always returns a ‘0’ for this bit since 10 returns 0 Mbps Half Duplex is not supported Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 132 This is due to the Auto-Negotiation state machine which requires that synchronization is lost for an entire link timer duration before changing state. For more information, see the 802.3 specification. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 133 Always return returns 0s 000000 number 3.3:0 Revision Number Always return returns 0s 0000 Register 15: Extended Status MDIO Register 15: Extended Status 15 14 13 12 11 Reg 15 Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 134 T Full Duplex is not supported 15.12 1000BASE-T Half Always returns a ‘0’ since 1000BASE- returns 0 Duplex T Half Duplex is not supported 15:11:0 Reserved Always return 0s returns 0s 0000000000 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 135: Sgmii Standard Using The Optional Auto-Negotiation

    SGMII Auto-Negotiation Next Page Receive Register SGMII Extended Status Register SGMII Vendor Specific: Auto-Negotiation Interrupt Control Register 0: SGMII Control MDIO Register 0: SGMII Control 15 14 13 12 11 10 Reg 0 Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 136 Always returns a ‘0’ for this bit to returns 0 disable COL test Speed Always returns a ‘1’ for this bit. returns 1 Selection Together with bit 0.13, speed (MSB) selection of 1000 Mbps is identified www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 137 0 Duplex 100BASE-T2 Half Duplex is not supported Extended Status Always returns a ‘1’ for this bit to indicate returns 1 the presence of the Extended Register (Register 15) Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 138 SGMII link. This is due to the Auto-Negotiation state machine which requires that synchronization is lost for an entire link timer duration before changing state. For more information, see the 802.3 specification. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 139 Table 9-22: SGMII Auto-Negotiation Advertisement (Register 4) Bit(s) Name Description Attributes Default Value 4.15:0 All bits SGMII defined value sent from read only 0000000000000001 the MAC to the PHY Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 140 11 = Reserved read only 10 = 1 Gbps 01 = 100 Mbps 00 = 10 Mbps 5.9:1 Reserved Always return 0s returns 0s 000000000 Reserved Always returns ‘1’ returns 1 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 141 1 = Additional Next Page(s) will follow read/ 0 = Last page write 7.14 Reserved Always returns ‘0’ returns 0 7.13 Message 1 = Message Page read/ Page 0 = Unformatted Page write Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 142 Toggle Value toggles between subsequent read only Next Pages 8.10:0 Message / Message Code Field or Unformatted read only 00000000000 Unformatted Page Encoding as dictated by 8.13 Code Field www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 143 15.12 1000BASE-T Always returns a ‘0’ for this bit since returns 0 Half Duplex 1000BASE-T Half Duplex is not supported 15:11:0 Reserved Always return 0s returns 0s 000000000000 Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 144 If the Interrupt is disabled, the bit is set to ‘0.’ NOTE: The an_interrupt port of the core is wired to this bit. 16.0 Interrupt 1 = Interrupt enabled read/ Enable 0 = Interrupt disabled write www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 145: Sgmii Standard Without The Optional Auto-Negotiation

    SGMII Status Register PHY Identifier SGMII Auto-Negotiation Advertisement Register SGMII Extended Status Register Register 0: SGMII Control MDIO Register 0: SGMII Control 15 14 13 12 11 10 Reg 0 Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 146 Always returns a ‘0’ for this bit to returns 0 disable COL test Speed Always returns a ‘1’ for this bit. returns 1 Selection Together with bit 0.13, speed (MSB) selection of 1000 Mbps is identified www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 147 0 Duplex 100BASE-T2 Half Duplex is not supported Extended Status Always returns a ‘1’ for this bit to indicate returns 1 the presence of the Extended Register (Register 15) Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 148 SGMII link. This is due to the Auto-Negotiation state machine which requires that synchronization is lost for an entire link timer duration before changing state. For more information, see the 802.3 specification. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 149 Reg 4 Table 9-33: SGMII Auto-Negotiation Advertisement (Register 4) Bit(s) Name Description Attributes Default Value 4.15:0 All bits Ignore this register because read only 0000000000000001 Auto-Negotiation is not included Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 150: Both 1000Base-X And Sgmii Standards

    “SGMII Standard Using the Optional Auto-Negotiation,” “SGMII Standard without the Optional Auto-Negotiation.” This register may be written to at any time. See Chapter 11, “Dynamic Switching of 1000BASE-X and SGMII Standards” for more information. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 151: Optional Configuration Vector

    Optional Configuration Vector “MDIO Management Interface” is omitted, relevant configuration signals are brought out of the core. These signals are bundled into the CONFIGURATION_VECTOR signal as defined in Table 9-36. Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 152 • When set to ‘0,’ normal operation is enabled. 1. Signals are synchronous to the core’s internal 125 MHz reference clock; this is userclk2 when used with a RocketIO transceiver; gtx_clk when used with TBI. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 153: Chapter 10: Auto-Negotiation

    IEEE 802.3 clause 37 describes the 1000BASE-X Auto-Negotiation function that allows a device to advertise the modes of operation that it supports to a device at the remote end of Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 154 Polling the Auto-Negotiation completion bit 1.5 in the Status Register (Register 1). ♦ Using the Auto-Negotiation interrupt port of the core (see “Using the Auto- Negotiation Interrupt,” page 156). www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 155: Sgmii Standard

    “MDIO Register 5: SGMII Auto-Negotiation Link Partner Ability,” page 140. There are no other differences and dealing with the results of Auto-Negotiation can be handled as described previously in “1000BASE-X Auto-Negotiation Overview.” Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 156: Setting The Configurable Link Timer

    Negotiation cycle. It will remain high until it is cleared by writing 0 to bit 16.1 (Interrupt Status bit) of the “MDIO Register 16: Vendor Specific Auto-Negotiation Interrupt Control,” page 129. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 157: Chapter 11: Dynamic Switching Of 1000Base-X And Sgmii Standards

    The core must operate in SGMII mode to provide BASE-T functionality and use the twisted copper pair. The GMII of the Ethernet 1000BASE-X PCS/PMA or SGMII core is shown connected to an embedded Ethernet Media Access Controller (MAC), for example the Tri-Mode Ethernet MAC core from Xilinx. 1000BASE-X Virtex-II Pro Device SGMII...

  • Page 158: Operation Of The Core

    • Switching the standard using MDIO. This does not cause Auto-Negotiation to automatically restart. Xilinx recommends that after switching to a new standard using a MDIO write, immediately perform the following: ♦ If you have switched to the 1000BASE-X standard, reprogram the Auto- Negotiation Advertisement Register (Register 4) to the desired settings.
  • Page 159 Auto-Negotiation cycle by the Link Timer when the core is set to perform the SGMII standard. Both ports follow the same rules that are described in “Setting the Configurable Link Timer,” page 156. Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 160 Chapter 11: Dynamic Switching of 1000BASE-X and SGMII Standards www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 161: Chapter 12: Constraining The Core

    Sections from the UCF are copied into the descriptions in the following sections to serve as examples. These should be studied in conjunction with Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 162 Special attention must be made to the placement of the SERDES alignment flip-flop as described in the RocketIO Transceiver User Guide (Chapter 2, SERDES Alignment, Ports, and Attributes, ENPCOMMAALIGN, ENMCOMMAALIGN). This is the single flip-flop illustrated in Figure 7-1. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 163: Virtex-Ii Pro Rocketio Mgts For Sgmii Or Dynamic Standards

    TIMEGRP "rxrecclk" AREA_GROUP = "local_clk"; AREA_GROUP "local_clk" RANGE = SLICE_X6Y56:SLICE_X15Y79; # Constrain the block RAM used for the fabric Rx Elastic # Buffer to be near the RocketIO INST "rocketio/clock_correction/dual_port_block_ram" LOC = RAMB16_X1Y8; Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 164: Virtex-4 Rocketio Mgts For 1000Base-X Constraints

    DCLK is a clock with a frequency between 25 and 50 MHz, which must be provided to the Dynamic Reconfiguration Port and to the calibration block of the MGT. In the example design, this is constrained to 50 MHz. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 165 "rxp0" LOC = J26; "rxn0" LOC = K26; "txp0" LOC = M26; "txn0" LOC = N26; "rxp1" LOC = U26; "rxn1" LOC = V26; "txp1" LOC = P26; "txn1" LOC = R26; Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 166: Virtex-4 Rocketio Mgts For Sgmii Or Dynamic Standards Switching Constraints

    (for Verilog design entry): these files were generated using the GTP Transceiver Wizard - to change the attributes, re-run the Wizard. “Virtex-5 RocketIO GTP Wizard” in Chapter www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 167: Virtex-5 Rocketio Gtp Transceivers For Sgmii Or Dynamic Standards

    DCM. The ports CLK0 (125MHz) and CLKDV (62.5MHz) of this DCM are then placed onto global clock routing to produce the usrclk2 and usrclk clock signals respectively. The Xilinx tools will trace the refclkout constraint through the DCM and automatically generate clock period constraints for the DCM output clocks. So constraints usrclk2 and usrclk do not need to be manually applied.

  • Page 168: Virtex-5 Rocketio Gtx Transceivers For Sgmii Or Dynamic Standards

    Sections from this UCF have been copied into the descriptions in this section to serve as examples, and should be studied with the HDL source code for the example design. See also Chapter 6, “The Ten-Bit Interface.” www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 169 INST "pma_tx_clk" IOSTANDARD = LVTTL; INST "rx_code_group<?>" IOSTANDARD = LVTTL; INST "pma_rx_clk0" IOSTANDARD = LVTTL; INST "loc_ref" IOSTANDARD = LVTTL; INST "ewrap" IOSTANDARD = LVTTL; INST "en_cdet" IOSTANDARD = LVTTL; Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 170 Virtex-II Pro family. Although not illustrated, these families have input delay elements (always of a fixed delay). These are also automatically inserted by the Xilinx tools and are set to provide a zero-hold time. These input delays automatically meet input setup and hold timing on the TBI without any specific constraints.
  • Page 171 The setup/hold timing which is achieved after place-and-route is reported in the datasheet section of the TRCE report (created by the implement script). See “Understanding Timing Reports for Setup/Hold Timing.” Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 172: Constraints When Implementing An External Gmii

    (gmii_tx_clk is used in the example design). This clock must be constrained for a clock frequency of 125 MHz. The following UCF syntax shows the necessary constraints being applied to the example design. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 173 In addition, the example design provides pad locking on the GMII for several families. This is a provided as a guideline only; there are no specific I/O location constraints for this core. Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 174 (which are always of a fixed delay). These are also automatically inserted by the Xilinx tools and are set to provide a zero-hold time. These input delays will automatically meet input setup and hold timing on the GMII without any specific constraints.
  • Page 175 The tap delays are applied using the following UCF syntax. #----------------------------------------------------------- # To Adjust GMII Tx Input Setup/Hold Timing #----------------------------------------------------------- INST "delay_gmii_tx_en" IDELAY_VALUE = "33"; INST "delay_gmii_tx_er" IDELAY_VALUE = "33"; INST "gmii_data_bus[7].delay_gmii_txd" IDELAY_VALUE = "33"; Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 176: Understanding Timing Reports For Setup/Hold Timing

    Timing Report. Note that initially, the results do not indicate an obvious relationship to Figure 12-2 Figure 12-3. The following example shows the GMII report from a Virtex-4 device. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 177 8 ns -6.501 ns = 8 - 6.501 SETUP = 1.499 ns = 7.893 - 8 HOLD = -0.107 ns 7.893 ns 8 ns Figure 12-4: Timing Report Setup/Hold Illustration Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 178 Chapter 12: Constraining the Core www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 179: Chapter 13: Interfacing To Other Cores

    This core supports full-duplex operation at 1 Gigabit per second. A description of and instructions for obtaining the newest 1-Gigabit Ethernet MAC core are located on the 1-Gigabit Ethernet MAC product page: www.xilinx.com/systemio/gmac/index.htm Integration of the 1-Gigabit Ethernet MAC to 1000BASE-X PCS with TBI Figure 13-1...
  • Page 180 Figure 13-1: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS with TBI www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 181: Integration Of The 1-Gigabit Ethernet Mac Using A Rocketio Transceiver

    1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and PMA Using a Virtex-II Pro MGT Features of this configuration include: • Direct internal connections are made between the GMII interfaces between the two cores. Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 182 RocketIO I/F mdio_in mdio_in mdio_out mdio_out mdio_tri mdio_tri connection Figure 13-3: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and PMA Using a Virtex-4 MGT www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 183 RocketIO I/F mdio_in mdio_in mdio_out mdio_out mdio_tri mdio_tri connection Figure 13-4: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and PMA Using a Virtex-5 GTP Transceiver Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 184 RocketIO I/F mdio_in mdio_in mdio_out mdio_out mdio_tri mdio_tri connection Figure 13-5: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and PMA Using a Virtex-5 GTX Transceiver www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 185: Integration Of The 1-Gigabit Ethernet Mac To Provide Sgmii

    A description of the latest available IP update containing the Tri-Mode Ethernet MAC core and instructions can be found in the Tri-Mode Ethernet MAC product Web page: www.xilinx.com/systemio/temac/index.htm Caution! The Tri-Mode Ethernet MAC should always be configured for full-duplex operation when used with an SGMII.
  • Page 186 This is the most efficient way to connect the two cores together in terms of clock resource usage and so is recommended. See the Tri-Mode Ethernet MAC User Guide for more information. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 187 Figure 13-6: Tri-Speed Ethernet MAC Extended to use an SGMII with TBI Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 188: Integration Of The Tri-Mode Ethernet Mac To Provide Sgmii (Or Dynamic Switching) Functionality Using Rocketio Transceivers

    This is the most efficient way to connect the two cores together in terms of clock resource usage and so is recommended. See the Tri-Mode Ethernet MAC User Guide for more information. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 189 Figure 13-7: Tri-Speed Ethernet MAC Extended to use an SGMII in Virtex-II Pro Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 190 This is the most efficient way to connect the two cores together in terms of clock resource usage and so is recommended. See the Tri-Mode Ethernet MAC User Guide for more information. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 191 Figure 13-8: Tri-Speed Ethernet MAC Extended to Use an SGMII in Virtex-4 Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 192 This is the most efficient way to connect the two cores together in terms of clock resource usage and so is recommended. See the Tri-Mode Ethernet MAC User Guide for more information. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 193 Figure 13-9: Tri-Speed Ethernet MAC Extended to use an SGMII in Virtex-5 LXT/SXT Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 194 This is the most efficient way to connect the two cores together in terms of clock resource usage and so is recommended. See the Tri-Mode Ethernet MAC User Guide for more information. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 195 Figure 13-10: Tri-Speed Ethernet MAC Extended to use an SGMII in Virtex-5 FXT Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 196 Chapter 13: Interfacing to Other Cores www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 197: Chapter 14: Special Design Considerations

    There is no physical loopback path in the core. Placing the core into loopback has the effect of asserting logic 1 on the ewrap signal of the TBI (see “1000BASE-X PCS with TBI Pinout,” Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 198: Core With Rocketio Transceiver

    LOOPBACK[1:0] input port of the RocketIO transceiver may be directly driven by the user logic to place it in either parallel or serial loopback mode. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 199 PCS/PMA or SGMII Core RocketIO Transceiver Idle Stream PCS Tx Engine PCS Rx Engine loopback control Loopback occurs in core Figure 14-2: Loopback Implementation When Using the Core with RocketIO Transceivers Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 200 Chapter 14: Special Design Considerations www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 201: Chapter 15: Implementing The Design

    Using the Simulation Model For information about setting up your simulator to use the pre-implemented model, please consult the Xilinx Synthesis and Verification Design Guide, included in your Xilinx software installation. The model is provided in the CORE Generator project directory.

  • Page 202: Xst - Verilog

    Implementation Generating the Xilinx Netlist To generate the Xilinx netlist, the ngdbuild tools is used to translate and merge the individual design netlists into a single design database—the NGD file. Also merged at this stage is the UCF for the design. An example of the ngdbuild command is: $ ngdbuild -sd path_to_core_netlist -sd path_to_user_synth_results \ -uc top_level_module_name.ucf top_level_module_name...

  • Page 203: Static Timing Analysis

    -tm netlist top_level_module_name.ncd \ top_level_module_name_postimp.v Using the Model For information about setting up your simulator to use the pre-implemented model, please consult the Xilinx Synthesis and Verification Design Guide, included in your Xilinx software installation. Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com...

  • Page 204: Other Implementation Information

    SWIFT-compliant simulator. ModelSim, Cadence IUS, and Synopsys are currently supported using the versions defined above. Other Implementation Information For more information about using the Xilinx implementation tool flow, including command line switches and options, consult the software manuals provided with the Xilinx ISE software.

  • Page 205: Appendix A: Core Verification, Compliance, And Interoperability

    • Clock Compensation in the Elastic Buffers Hardware Verification The core has been tested in a variety of hardware test platforms at Xilinx to represent different parameterizations, including the following: • The core with RocketIO transceiver and performing the 1000BASE-X standard was tested with the 1-Gigabit Ethernet MAC core from Xilinx.
  • Page 206 Appendix A: Core Verification, Compliance, and Interoperability www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 207: Appendix B: Core Latency

    Ethernet MAC core that is within the IEEE specified latency for a MAC sublayer. For example, when the core is connected to the Xilinx 1-Gigabit Ethernet MAC core, the system as a whole is compliant with the overall IEEE 802.3 latency specifications.

  • Page 208: Latency For 1000Base-X Pcs And Pma Using A Rocketio Transceiver

    When performing the SGMII standard, the core latency figures are identical to the Latency for 1000BASE-X PCS and PMA using the MGT. Again these figures do not include the latency through the MGT or any Elastic Buffers added in the example design. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 209: Appendix C: Calculating The Dcm Fixed Phase Shift Value

    System Margin (ps) = UI(ps) * (working phase shift range/128) Finding the Ideal Phase Shift Value for Your System Xilinx cannot recommend a singular phase shift value that is effective across all hardware platforms. Xilinx does not recommend attempting to determine the phase shift setting empirically.
  • Page 210 During the production test, Xilinx recommends that you re-examine the working range at corner case operating conditions to determine whether any adjustments to the final phase shift setting are needed.

  • Page 211: Introduction

    Correcting /I1/, Preserving /I2/ /I1/ IDLE_1 /K28.5/D5.6/ /I2/ IDLE_2 /K28.5/D16.2/ Encapsulation Carrier_Extend /K23.7/ Start_of_Packet /K27.7/ End_of_Packet /K29.7/ Error_Propagation /K30.7/ 1. Two data code-groups representing the Config_Reg value (contains Auto-Negotiation information) Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 212: Start Of Frame Encoding

    Packet code group /S/ following the Idle (in the even position). This is inserted in place of the first byte of the frame preamble field. gmii_txd[7:0] preamble gmii_tx_en gmii_tx_er PCS Transmit Engine Encoding tx_code_group preamble Figure D-1: 1000BASE-X Transmit State Machine Operation (Even Case) www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 213: Reception Of The Even Case

    /D16.2/ character of the Idle /I2/ sequence being inserted in place of the first byte of the preamble field, and the Start-Of-Packet /S/ being inserted in place of the second byte of preamble as illustrated. Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 214: Reception Of The Odd Case

    This has resulted in a single byte of preamble loss across the system. rx_code_group I2 preamble PCS Receive Engine Decoding gmii_rxd[7:0] preamble gmii_rx_dv gmii_rx_er Figure D-4: 1000BASE-X Reception State Machine Operation (Odd Case) www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 215: Preamble Shrinkage

    /I2/ if the frame ended with negative running disparity. This is illustrated as the shaded code group. gmii_txd[7:0] gmii_tx_en gmii_tx_er PCS Transmit Engine Encoding tx_code_group T R I1/I2 Figure D-5: 1000BASE-X Transmit State Machine Operation (Even Case) Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 216: Reception Of The Even Case

    Carrier Extend code groups /R/. This allows the /K28.5/ character of the following Idle code group to be aligned to the even position. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 217: Reception Of The Odd Case

    GMII encoding of Frame Extension. This occurs even in full-duplex mode. I1/I2 rx_code_group PCS Receive Engine Decoding gmii_rxd[7:0] 0x0F gmii_rx_dv gmii_rx_er Figure D-8: 1000BASE-X Reception State Machine Operation (Odd Case) Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 218 Appendix D: 1000BASE-X State Machines www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 219: Appendix E: Rx Elastic Buffer Specifications

    Virtex-II Pro, Virtex-4 FX, Virtex-5 LXT, SXT and FXT families. Each FIFO word corresponds to a single character of data (equivalent to a single byte of data following 8B10B decoding). Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 220 Table E-1: Maximum Frame Sizes: RocketIO Transceiver Rx Elastic Buffers (100ppm Clock Tolerance) Standard / Speed Maximum Frame Size 1000BASE-X (1 Gbps only) 90000 SGMII (1 Gbps) 90000 SGMII (100 Mbps) 9000 SGMII (10 Mbps) www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 221 Virtex-II Pro/Virtex-5 analysis. For this reason, by adjusting the threshold attributes accordingly, Table E-1 is also applicable. Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 222: Sgmii Fabric Rx Elastic Buffer

    Ethernet speeds. At SGMII speeds lower than 1 Gbps, performance is diminished because bytes are repeated multiple times (see “Designing with Client-side GMII for the SGMII Standard” in Chapter www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 223: Tbi Rx Elastic Buffer

    • If the buffer is emptying during reception, then there are 14-2 = 12 FIFO locations available before the buffer reaches the underflow mark. Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 224: Clock Correction

    Frame Sizes” section. However, since the legal maximum frame size for Ethernet frames is 1522 bytes (for a VLAN frame), idle character removal restrictions are not usually an issue. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...
  • Page 225 20000 bytes. However, this is larger than the maximum frame size for any Elastic Buffer provided with the core (see “Rx Elastic Buffers: Depths and Maximum Frame Sizes”). Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...

  • Page 226: Maximum Frame Sizes For Sustained Frame Reception

    Ethernet frame allowed in the IEEE 802.3 specification. The size of jumbo frames that can be reliably received is identical to the frame sizes defined in “Maximum Frame Sizes for Sustained Frame Reception,” page 226. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 227: Appendix F: Debugging Guide

    Appendix F Debugging Guide This appendix provides assistance for debugging the core within a system. For additional help, contact Xilinx by submitting a WebCase at support.xilinx.com/. General Checks • Ensure that all the timing constraints for the core were met during Place and Route.

  • Page 228: Problems With Auto-Negotiation

    When signal_detect is set to logic ‘0,’ this forces the receiver synchronization state machine of the core to remain in the loss of sync state. ♦ See the following section, “Problems with a High Bit Error Rate.” www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

  • Page 229: Problems With A High Bit Error Rate

    PCB problem. • Try swapping the optical module on a misperforming device and repeat the tests. Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com UG155 March 24, 2008...
  • Page 230 For Virtex-II Pro RocketIO only, check that the SERDES alignment logic is properly constrained to be placed near the RocketIO. See the Virtex-II Pro RocketIO Transceiver User Guide for more information. This constraint is not automatically adjusted for different RocketIO locations. www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 UG155 March 24, 2008...

This manual is also suitable for:

Logicore ip ethernet 1000base-x pcs/pma or sgmii v9.1

Table of Contents