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Table of Contents
Related Manuals for Xilinx LogiCORE IP CAN 3.2
Summary of Contents for Xilinx LogiCORE IP CAN 3.2
- Page 1 LogiCORE™ IP CAN v3.2 Getting Started Guide UG186 April 19, 2010...
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Page 2: Revision History
Xilinx is providing this product documentation, hereinafter “Information,” to you “AS IS” with no warranty of any kind, express or implied. Xilinx makes no representation that the Information, or any particular implementation thereof, is free from any claims of infringement. You are responsible for obtaining any rights you may require for any implementation based on the Information. -
Page 3: Table Of Contents
Timing Simulation ............16 CAN Getting Started Guide www.xilinx.com UG186 April 19, 2010... - Page 4 Customizing the Demonstration Test Bench ........27 www.xilinx.com...
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Page 5: Schedule Of Figures
Figure 4-2: Demonstration Test Bench ......... . . 25 CAN Getting Started Guide www.xilinx.com UG186 April 19, 2010... - Page 6 CAN Getting Started Guide UG186 April 19, 2010...
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Page 7: Preface: About This Guide
About This Guide The CAN v3.2 Getting Started Guide provides information about generating the LogiCORE™ IP CAN core, customizing and simulating the core with the provided example design, and running the design files through implementation using the Xilinx tools. Guide Contents The following chapters are included in this guide: •... -
Page 8: Online Document
Blue text location in the current “Title Formats” in Chapter 1 document for details. Go to www.xilinx.com for the Blue, underlined text Hyperlink to a website (URL) latest speed files. www.xilinx.com CAN Getting Started Guide UG186 April 19, 2010... -
Page 9: Chapter 1: Introduction
Xilinx. About the Core The CAN core is a Xilinx CORE Generator™ IP core, included in the latest IP Update on the Xilinx IP Center. For detailed information about the core, see www.xilinx.com/xlnx/xebiz/designResources/ip_product_details. -
Page 10: Recommended Design Experience
For technical support, visit www.support.xilinx.com. Questions are routed to a team of engineers with expertise using the CAN core. Xilinx will provide technical support for use of this product as described in this guide. Xilinx cannot guarantee timing, functionality, or support of this product for designs that do not follow these guidelines. -
Page 11: Chapter 2: Licensing The Core
License Options The CAN core provides three licensing options. After installing the required Xilinx ISE® software and IP Service Packs, choose a license option. Simulation Only The Simulation Only Evaluation license key is provided with the Xilinx CORE Generator™... -
Page 12: Full
Click Evaluate. Follow the instructions to install the required Xilinx ISE software and IP Service Packs. Obtaining a Full License To obtain a Full license key, you must purchase a license for the core. After doing so, click the “Access Core”... -
Page 13: Chapter 3: Quick Start Example Design
Quick Start Example Design This chapter provides instructions to generate a CAN core quickly, run the design through implementation with the Xilinx tools, and simulate the example design using the provided demonstration test bench. See the example design in Chapter 4, “Detailed Example Design.”... -
Page 14: Generating The Core
Chapter 3: Quick Start Example Design Generating the Core This section describes how to generate a CAN core with default values using the Xilinx CORE Generator™ tool. To generate the core: Start the CORE Generator tool. For help starting and using the CORE Generator tool, see the Xilinx CORE Generator... -
Page 15: Implementing The Example Design
CORE Generator software Design Entry project option. Setting up for Simulation The Xilinx UniSim and SimPrim libraries must be mapped into the simulator. If the UniSim or SimPrim libraries are not set for your environment, go to the Synthesis and Simulation... -
Page 16: Functional Simulation
This section contains instructions for running a timing simulation of the CAN core using either VHDL or Verilog. A timing simulation model is generated when the core is run through the Xilinx tools using the implement script. It is a requirement that the core is implemented before attempting to run timing simulation. -
Page 17: Chapter 4: Detailed Example Design
Detailed Example Design This chapter provides detailed information about the example design, including a description of files and the directory structure generated by the Xilinx CORE Generator™ software, the purpose and contents of the provided scripts, the contents of the example HDL wrappers, and the operation of the demonstration test bench. -
Page 18: Directory And File Contents
The <component name> directory contains the release notes file provided with the core, which may include last-minute changes and updates. Table 4-2: Component Name Directory Name Description <project_dir>/<component_name> Core name release notes file. can_release_notes.txt Back to Top www.xilinx.com CAN Getting Started Guide UG186 April 19, 2010... -
Page 19: Component_Name>Example Design
Name Description <project_dir>/<component_name>/example_design Provides example constraints necessary for <component_name>_top.ucf processing the CAN core using the Xilinx implementation tools. The VHDL or Verilog top-level file for the <component_name>_top.v[hd] example design; it instantiates the CAN core. Top-level file for the example design. Only <component_name>.v... -
Page 20: Component_Name>/Implement
The simulation directory contains the simulation scripts provided with the core. Table 4-7: Simulation Directory Name Description <project_dir>/<component_name>/simulation Verilog test file provided with the glbl.v demonstration test bench. Verilog/VHDL test file provided with the can_v3_2_tb.v[hd] demonstration test bench. Back to Top www.xilinx.com CAN Getting Started Guide UG186 April 19, 2010... -
Page 21: Component_Name>/Simulation/Functional
A macro file for Cadence IES that opens a wave.sv wave window and adds key signals to the wave viewer. Back to Top CAN Getting Started Guide www.xilinx.com UG186 April 19, 2010... -
Page 22: Simulation/Timing
A macro file for Cadence IES that opens a wave.sv wave window and adds key signals to the wave viewer. Back to Top www.xilinx.com CAN Getting Started Guide UG186 April 19, 2010... -
Page 23: Implementation Scripts
Design Entry project setting) and timing information in the form of SDF files The Xilinx tool flow generates several output and report files. These are saved in the following directory which is created by the implement script: <project_dir>/<component_name>/implement/results... -
Page 24: Timing Simulation
During simulation, the CAN core is instantiated as a black box and replaced with the CORE Generator software netlist during implementation and the gate-level simulation model. • Input and output buffers for top-level port signal www.xilinx.com CAN Getting Started Guide UG186 April 19, 2010... -
Page 25: Demonstration Test Bench
• The Software Reset Register is written to enable CEN bit. This register is read from and the value written is compared with the value read. CAN Getting Started Guide www.xilinx.com UG186 April 19, 2010... - Page 26 The RX FIFO is read if the RXOK bit is set. The message that is received is compared with the message that was transmitted. ♦ The ICR is written to. This clears the bits in the ISR that are set. www.xilinx.com CAN Getting Started Guide UG186 April 19, 2010...
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Page 27: Customizing The Demonstration Test Bench
You can add messages using the following steps. Write the message to the TX FIFO. Wait for an interrupt and process the interrupt. Read the received message from the RX FIFO. CAN Getting Started Guide www.xilinx.com UG186 April 19, 2010... - Page 28 Chapter 4: Detailed Example Design www.xilinx.com CAN Getting Started Guide UG186 April 19, 2010...