Figure 8-3: Sgmii Connection To A Virtex-Ii Pro Rocketio Transceiver - Xilinx LogiCORE 1000BASE-X User Manual

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Chapter 8: SGMII / Dynamic Standards Switching with RocketIO Transceivers
IOB LOGIC
brefclkp
IBUFGDS
IPAD
brefclk (62.5MHz)
IPAD
brefclkn
DCM
BUFG
CLKIN CLK0
BUFG
FB
CLK2X180
LOCKED
component_name_block
(Block Level from
example design)

Figure 8-3: SGMII Connection to a Virtex-II Pro RocketIO Transceiver

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userclk (62.5MHz)
userclk2 (125MHz)
Ethernet 1000BASE-X
PCS/PMA or SGMII
LogiCORE
userclk
userclk2
dcm_locked
powerdown
txchardispmode
txchardispval
txcharisk
txdata[7:0]
mgt_rx_reset
mgt_tx_reset
rxbufstatus[1:0]
FPGA
rxchariscomma
fabric
rxcharisk
Rx
rxclkcorcnt[2:0] Elastic
Buffer
rxdata[7:0]
rxdisperr
enablealign
local
clock
routing
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
Virtex-II Pro
RocketIO
(GT_CUSTOM)
REFCLKSEL
REFCLK
NC
GND
REFCLK2
NC
BREFCLK
NC BREFCLK2
TXUSRCLK
TXUSRCLK2
GND
LOOPBACK[1:0]
POWERDOWN
TXCHARDISPMODE
TXCHARDISPVAL
TXCHARISK
TXDATA[7:0]
RXRESET
TXRESET
RXCHARISCOMMA[1:0]
RXCHARISK[1:0]
RXDATA[15:0]
RXDISPERR[1:0]
RXUSRCLK
RXUSRCLK2
ENPCOMMAALIGN
D Q
ENMCOMMAALIGN
RXRECCLK
RXPOLARITY
TXPOLARITY
TXFORCECRCERR
TXINHIBIT
GND
UG155 March 24, 2008