Sgmii Standard Using The Optional Auto-Negotiation - Xilinx LogiCORE 1000BASE-X User Manual

Management Registers

SGMII Standard Using the Optional Auto-Negotiation

The registers provided for SGMII operation in this core are adaptations of those defined in
IEEE 802.3 clauses 37 and 22. In an SGMII implementation, two different types of links
exist. They are the SGMII link between the MAC and PHY (SGMII link) and the link across
the Ethernet Medium itself (Medium). See
Information regarding the state of both of these links is contained within the following
registers. Where applicable, the abbreviations SGMII link and Medium are used in the
register descriptions. Registers at undefined addresses are read-only and return 0s.
Table 9-18: MDIO Registers for 1000BASE-X with Auto-Negotiation
Register 0: SGMII Control
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Register Address
0
1
2,3
4
5
6
7
8
15
16
15 14 13 12 11 10
Reg 0
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Figure 10-2.
Register Name
SGMII Control Register
SGMII Status Register
PHY Identifier
SGMII Auto-Negotiation Advertisement Register
SGMII Auto-Negotiation Link Partner Ability Base Register
SGMII Auto-Negotiation Expansion Register
SGMII Auto-Negotiation Next Page Transmit Register
SGMII Auto-Negotiation Next Page Receive Register
SGMII Extended Status Register
SGMII Vendor Specific: Auto-Negotiation Interrupt Control
MDIO Register 0: SGMII Control
9 8 7 6 5 4 0
R
135