Receiver Logic - Xilinx LogiCORE 1000BASE-X User Manual

R
IOB LOGIC
IBUFG
gtx_clk
IPAD
component_name _block (Block Level from example design)
Ethernet 1000BASE-X PCS/PMA
or SGMII LogiCORE

Receiver Logic

Virtex-II and Virtex-II Pro Devices
Figure 6-2
logic displayed precisely match those delivered with the example design when the TBI is
chosen.
Figure 6-2
Rate (DDR) input registers, alternatively on the rising edges of both pma_rx_clk0_bufg
and pma_rx_clk1_bufg (pma_rx_clk0 and pma_rx_clk1 are 180 degrees out of
phase with each other). This splits the input TBI data bus, rx_code_group[9:0], up into
two buses: rx_code_group0_reg[9:0] and rx_code_group1_reg[9:0],
70
BUFG
gtx_clk_ibufg
gtx_clk_bufg
(125 MHz)
gtx_clk
tx_code_group_int[0]
tx_code_group[0]
tx_code_group_int[9]
tx_code_group[9]
Figure 6-1: Ten-Bit Interface Transmitter Logic
illustrates an external receiver TBI in Virtex-II devices. The signal names and
shows that the input receiver signals are registered in device IOB Double-Data
www.xilinx.com
Chapter 6: The Ten-Bit Interface
IOB LOGIC
FDDRRSE
'0'
D Q
pma_tx_clk_obuf
'1'
D Q
tx_code_group_reg[0]
D Q
tx_code_group_reg[9]
D Q
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
OBUF
pma_tx_clk
OPAD
OBUF
tx_code_group[0]
OPAD
OBUF
tx_code_group[9]
OPAD
UG155 March 24, 2008