Xilinx LogiCORE 1000BASE-X User Manual page 34

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MDIO Management Interface Pinout (Optional)
Table 2-3
Management Registers. These signals are typically connected to the MDIO port of a MAC
device, either off-chip or to an internally integrated MAC core. For more information, see
"Management Registers" in Chapter
Table 2-3: Optional MDIO Interface Signal Pinout
1. These signals can be connected to a Tri-state buffer to create a bidirectional mdio signal suitable for
34
describes the optional MDIO interface signals of the core used to access the PCS
Signal Direction
mdc Input
1
mdio__in Input
1
mdio_out Output
1
mdio_tri Output
phyad[4:0] Input
connection to an external MDIO controller (for example, an Ethernet MAC).
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9.
Clock
Domain
N/A Management clock (<= 2.5 MHz).
mdc Input data signal for communication with
MDIO controller (for example, an Ethernet
MAC). Tie high if unused.
mdc Output data signal for communication with
MDIO controller (for example, an Ethernet
MAC).
mdc Tri-state control for MDIO signals; '0' signals
that the value on mdio_out should be asserted
onto the MDIO interface.
N/A Physical Address of the PCS Management
register set. It is expected that this signal will be
tied off to a logical value.
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
Chapter 2: Core Architecture
Description
UG155 March 24, 2008