Xilinx LogiCORE 1000BASE-X User Manual page 130

R
Register 0: Control Register
Table 9-14: Control Register (Register 0)
130
15 14 13 12 11 10
Reg 0
Bit(s) Name
0.15 Reset 1 = PCS/PMA reset
0 = Normal Operation
0.14 Loopback 1 = Enable Loopback Mode
0 = Disable Loopback Mode
When used with a RocketIO transceiver,
the core is placed in internal loopback
mode.
With the TBI version, Bit 1 is connected to
ewrap. When set to '1' indicates to the
external PMA module to enter loopback
mode.
See
0.13 Speed Always returns a 0 for this bit. Together
Selection with bit 0.6, speed selection of 1000 Mbps
(LSB) is identified.
0.12 Auto- Ignore this bit because Auto-Negotiation
Negotiation is not included.
Enable
0.11 Power Down 1 = Power down
0 = Normal operation
With the PMA option, when set to '1' the
RocketIO transceiver is placed in a low-
power state. This bit requires a reset (see
bit 0.15) to clear.
With the TBI version this register bit has
no effect.
0.10 Isolate 1 = Electrically Isolate PHY from GMII
0 = Normal operation
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Chapter 9: Configuration and Status
MDIO Register 0: Control Register
9 8 7 6
Description
"Loopback," page 197.
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
5 4 0
Attributes
read/write
self clearing
read/write
returns 0 0
read/ write
read/ write
read/write
UG155 March 24, 2008
Default
Value
0
0
1
0
1