Xilinx LogiCORE 1000BASE-X User Manual page 27

Core Interfaces
functionality. For more information, see
Core."
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
GMII gmii_txd[7:0]
gmii_tx_en
gmii_tx_er
gmii_rxd[7:0]
gmii_rx_dv
gmii_rx_er
gmii_isolate
MDIO
mdc
mdio_in
mdio_out
mdio_tri
phyad[4:0]
reset
gtx_clk
Auto_Negotiation
an_interrupt
link_timer_value[8:0]
Figure 2-3: Component Pinout Using RocketIO Transceiver
with PCS Management Registers
www.xilinx.com
Chapter 3, "Generating and Customizing the
RocketIO Interface
mgt_rx_reset
mgt_tx_reset
userclk
userclk2
dcm_locked
rxbufstatus[1:0]
rxchariscomma
rxcharisk
rxclkcorcnt[2:0]
rxdata[7:0]
rxdisperr
rxnotintable
rxrundisp
txbuferr
powerdown
txchardispmode
txchardispval
txcharisk
txdata
enablealign
signal_detect
status_vector[4:0]
R
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