Multiple Core Special Considerations; Dts Domain For Quad-Core Intel® Xeon® Processor 5300 Series - Intel X5365 - Xeon 3.0 GHz 8M L2 Cache 1333MHz FSB LGA771 Quad-Core Processor Design Manual

Thermal/Mechanical Reference Design
2.2.4

Multiple Core Special Considerations

2.2.4.1 Multiple Digital Thermal Sensor Operation
Each Quad-Core Intel® Xeon® Processor 5300 Series processor can have multiple
Digital Thermal Sensors located on the die. Each die within the processor currently
maps to a PECI domain. The Quad-Core Intel® Xeon® Processor 5300 Series contains
two dies (Domains) and each die contains two cores. BIOS will be responsible for
detecting the proper processor type and providing the number of domains to the
thermal management system. An external PECI device that is part of the thermal
management system polls the processor domains for temperature information and
currently receives the highest of the DTS output temperatures within each domain.
Figure 2-5
Processor 5300 Series.
Figure 2-5. DTS Domain for Quad-Core Intel® Xeon® Processor 5300 Series
Core_1 Core_1 Core_1
DTS_1 DTS_1 DTS_1
2.2.4.2 Thermal Monitor for Multiple Core Products
The thermal management for multiple core products has only one T
processor. The T
from each other. If the DTS temperature from any domain within the processor is
greater than or equal to T
below the temperature as specified by the thermal profile. See
information on T
LAG771 socket for the Quad-Core Intel® Xeon® Processor 5300 Series. Through this
pin, the dual domains receive all temperature sensor values and provide the current
hottest value to an external PECI device such as a thermal management system.
Quad-Core Intel® Xeon® Processor 5300 Series Thermal/Mechanical Design Guidelines (TMDG)
provides an illustration of the DTS domains for the Quad-Core Intel® Xeon®
Domain 1 Domain 1 Domain 1
Domain 0 Domain 0 Domain 0
Core_2 Core_2 Core_2 Core_3 Core_3 Core_3
DTS_3 DTS_3 DTS_3
DTS_2 DTS_2 DTS_2
Socket 0 Socket 0 Socket 0
T T for for
CONTROL CONTROL
Processor 0 Processor 0
for processor 0 and T
CONTROL
CONTROL
. The PECI signal is available through CPU pin (G5) on each
CONTROL
Fan Speed Controller Fan Speed Controller Fan Speed Controller
PECI Host PECI Host PECI Host
Domain 0 Domain 0
Core_4 Core_4 Core_4 Core_1 Core_1 Core_2 Core_2
DTS_1 DTS_1
DTS_4 DTS_4 DTS_4
for processor 1 are independent
CONTROL
, the processor case temperature must remain at or
Domain 1 Domain 1
Core_3 Core_3 Core_4 Core_4
DTS_3 DTS_3
DTS_2 DTS_2 DTS_4 DTS_4
Socket 1 Socket 1
T T for for
CONTROL CONTROL
Processor 1 Processor 1
value per
CONTROL
Section 2.2.6 for
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