Digital Thermal Sensor; Platform Environmental Control Interface (Peci) - Intel X5365 - Xeon 3.0 GHz 8M L2 Cache 1333MHz FSB LGA771 Quad-Core Processor Design Manual

from a power perspective. These applications are then evaluated in a controlled
thermal environment to determine their sensitivity to activation of the thermal control
circuit. This data set is then used to derive the TDP targets published in the processors
Datasheet. The Thermal Monitor can protect the processors in rare workload excursions
above TDP. Therefore, thermal solutions should be designed to dissipate this target
power level. The thermal management logic and thermal monitor features are
discussed in extensive detail in the Quad-Core Intel® Xeon® Processor 5300 Series
Datasheet.
In addition, on-die thermal management features called THERMTRIP# and FORCEPR#
are available on the Quad-Core Intel® Xeon® Processor 5300 Series. They provide a
thermal management approach to support the continued increases in processor
frequency and performance. Please see the Quad-Core Intel® Xeon® Processor 5300
Series Datasheet for guidance on these thermal management features.
2.2.2

Digital Thermal Sensor

The Quad-Core Intel® Xeon® Processor 5300 Series include on-die temperature
sensor feature called Digital Thermal Sensor (DTS). The DTS uses the same sensor
utilized for TCC activation. Each individual processor is calibrated so that TCC activation
occurs at a DTS value of 0. The temperature reported by the DTS is the relative offset
in PECI counts below the onset of the TCC activation temperature and hence is
negative. Changes in PECI counts are roughly linear in relation to temperature changes
in degrees Celsius. For example, a change in PECI count by '1' represents a change in
temperature of approximately 1°C. However, this linearity cannot be guaranteed as the
offset below TCC activation exceeds 20-30 PECI counts. Also note that the DTS will not
report any values above the TCC activation temperature, it will simply return 0 in this
case.
The DTS also facilitates the use of multiple thermal sensors within the processor
without the burden of increasing the number of thermal sensor signal pins on the
processor package. Operation of multiple DTS will be discussed more detail in
Section 2.2.4. Also, the DTS utilizes thermal sensors that are optimally located when
compared with thermal diodes available with legacy processors. This is achieved as a
result of a smaller foot print and decreased sensitivity to noise. These DTS benefits will
result in more accurate fan speed control and TCC activation. The DTS application in
fan speed control will be discussed more detail in
2.2.3

Platform Environmental Control Interface (PECI)

The PECI interface is designed specifically to convey system management information
from the processor (initially, only thermal data from the Digital Thermal Sensor). It is a
proprietary single wire bus between the processor and the chipset or other health
monitoring device. The PECI specification provides a specific command set to discover,
enumerate devices, and read the temperature. For an overview of the PECI interface,
please refer to PECI Feature Set Overview. For more detail information on PECI, please
refer to Platform Environment Control Interface (PECI) Specification and Quad-Core
Intel® Xeon® Processor 5300 Series Datasheet.
20 Quad-Core Intel® Xeon® Processor 5300 Series Thermal/Mechanical Design Guidelines (TMDG)
Thermal/Mechanical Reference Design
Section 2.3.1.