7: Panel Status Holding Register; Analog Values Input Registers; 1: Panel And System Troubles Holding Registers - Honeywell HON-CGW-MBB Installation And User Manual

Analog Values Input Registers

7.22.7 Panel Status Holding Register
The panel status holding register is divided into an upper and lower byte as described
below and in
register address as shown in
• Silence: The fire alarm control panel is silenced when this bit is set to 1.
• Reset: Not used.
Bit No. 15
Bit
Name
Start Address
7.23 Analog Values Input Registers
Analog values listed in
20 mA modules. Refer to
analog values.
7.23.1 Panel and System Troubles Holding Registers
One hundred 16-bit registers are reserved for panel troubles and one register is assigned
as an overall panel trouble indicator as shown in
Holding Register
Start Address
460000
460001
A single bit is reserved for each trouble in the system. The assignment of bits to trouble
codes is shown in
CLSS Gateway - Installation and Users' Manual | P/N:LS10248-000HW-E | REV. F | FEB/11/2022
Table 7.21, "Panel Status Holding Register Bit Definitions"
Table 7.22, "Panel Status Holding Register
Table 7.21: Panel Status Holding Register Bit Definitions
Upper Byte
14 13 12
Table 7.22: Panel Status Holding Register Addresses
End Address
420001 420001
Table 7.23, "Input Register Analog Values"
Table 7.23, "Input Register Analog Values"
Table 7.23: Input Register Analog Values
Start Address
310001
310301
310601
310901
311201
311501
311801
312101
312401
312701
Addresses".
Table 7.24: Panel and System Troubles Holding Register Addresses
End Address
460000
460100
Table 7.33: "System Troubles Register Map"
11 10 9 8 7
Not Used
Panel Status Holding Register
End Address
310300
310600
310900
311200
311500
311800
312100
312400
312700
313000
Table 7.24, "Panel and System Troubles
Panel Trouble Summary
(Total number of Trouble bits set for the node)
Panel Troubles
Modbus Communications
representing one
Addresses".
Lower Byte
6 5 4 3 2
Description
are only available for 4–
for details regarding
Analog Value
(16 bits)
L1M1–L1M300
L2M1–L2M300
L3M1–L3M300
L4M1–L4M300
L5M1–L5M300
L6M1–L6M300
L7M1–L7M300
L8M1–L8M300
L9M1–L9M300
L10M1–L10M300
Description
.
1 0
Silence Reset
67