Sram; Cache And Memory - AOpen AP55CS User Manual

AMI BIOS

SRAM

Cache Tag Size
This parameter lets you set the tag size that your cache supports.
The selections are 7 bits and 8 bits. The default is .
8 bits

Cache and Memory

Noncacheable Block (1 and 2)
This feature allows you to allocate the memory to either DRAM or
PCI bus. The options are DRAM, PCI bus and Disabled. Select
to reserve the total memory area for system use. Select
DRAM PCI
bus to reserve the memory area for I/O or add-on card use. Select
Disabled to disregard the feature.
BLOCK SIZE
This parameter lets you set the memory size reserved to either
system use or add-on card use. The available settings are 64 KB,
128 KB, 256 KB, 572 KB, 1 MB, 2 MB, 4 MB, and 8 MB.
BLOCK BASE ADDRESS
This parameter lets you set the starting address where you want to
relocate the memory. The memory selections depend on the
selected block size. For example, if the Block Size is set to 128 KB,
the memory selections are in multiples of 128 i.e., 0 KB, 128 KB, 256
KB, etc. You can move from one selection to another by pressing +
or - .
4-24 User's Guide