Table of Contents
Advertisement
A
X
4
5
P
r
o
-
5
3
3
A
X
4
5
P
r
o
-
5
3
3
P
B
S
R
A
M
(
P
i
p
e
l
i
n
e
d
P
B
S
R
A
M
(
P
i
p
e
l
i
n
e
For Socket 7 CPU, one burst data read requires four QWord (Quad-word, 4x16 = 64 bits). PBSRAM only needs one address decoding time
and automatically sends the remaining QWords to CPU according to a predefined sequence. Normally, it is 3-1-1-1, total 6 clocks, which is
faster than asynchronous SRAM. PBSRAM is often used on L2 (level 2) cache of Socket 7 CPU. Slot 1 and Socket 370 CPU do not need
PBSRAM.
P
C
-
1
0
0
D
I
M
M
P
C
-
1
0
0
D
I
M
M
SDRAM
DIMM that supports 100MHz CPU
P
C
-
1
3
3
D
I
M
M
P
C
-
1
3
3
D
I
M
M
SDRAM
DIMM that supports 133MHz CPU
P
C
-
1
6
0
0
o
r
P
C
-
2
1
0
P
C
-
1
6
0
0
o
r
P
C
-
2
1
0
Based on FSB frequency, the DDR DRAM has 200MHz and 266MHz two type of working frequency. Because of DDR DRAM data bus is
64-bit, it provides data transfer bandwidth up to 200x64/8=1600MB/s, and 266x64/8=2100MB/s. Hence, the PC-1600 DDR DRAM is
working with 100MHz and PC-2100 DDR DRAM is working with 133MHz FSB frequency.
P
C
I
(
P
e
r
i
p
h
e
r
a
l
C
o
m
P
C
I
(
P
e
r
i
p
h
e
r
a
l
C
o
Bus for the internal connection of peripheral devices, high-speed data channel between the computer and expansion card.
B
u
r
s
t
S
R
A
M
)
d
B
u
r
s
t
S
R
A
M
)
FSB
bus clock.
FSB
bus clock.
0
D
D
R
D
R
A
M
0
D
D
R
D
R
A
M
p
o
n
e
n
t
I
n
t
e
r
f
a
c
e
)
m
p
o
n
e
n
t
I
n
t
e
r
f
a
c
e
)
B
u
s
B
u
s
93
O
n
l
i
n
e
M
a
n
u
a
l
O
n
l
i
n
e
M
a
n
u
a
l
Advertisement
Table of Contents
