Panasonic FP0R User Manual page 190

Control code settings
Bits 0–15 of the control code are allocated in groups of four. The bit setting in each group is
represented by a hex number (e.g. 0002 0000 0000 1001 = 16#2009).
15 12 11
IV III
Group IV Channel number (channel n: 16#n)
1
Group III 0 (fixed)
Group II 0 (fixed)
Clear high-speed counter instruction (bit 3)
2
0: continue
Reset input (bit 2) (see note)
3
0: enabled
Group I
Count (bit 1)
4
0: permit
Reset elapsed value to 0 (bit 0)
5
0: no
Example: 16#2009
Group Value Description
IV 2 Channel number: 2
III 0 (fixed)
II 0 (fixed)
Hex 9 corresponds to binary 1001
Clear high-speed counter instruction: clear (bit 3) 1
I 9
Reset input: enabled (bit 2)
Count: permit (bit 1)
Reset elapsed value to 0: yes (bit 0)
NOTE
Use the reset input setting (bit 2) to disable the reset input allocated in the
system registers.
REFERENCE
Please refer to the FPWIN Pro online help for programming examples.
8 7 4 3
II
1: clear
1: disabled
1: prohibit
1: yes
High-Speed Counter and Pulse Output
0
I
0
0
1
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