Analog Input Timing Signals - National Instruments DAQ X Series User Manual

Chapter 4 Analog Input
common-mode rejection ratio (CMRR). These methods are outlined in the
Connecting Analog Input Signals
AI GND is an AI common signal that routes directly to the ground
connection point on the devices. You can use this signal if you need a
general analog ground connection point to the device.

Analog Input Timing Signals

In order to provide all of the timing functionality described throughout this
section, Simultaneous MIO X Series devices have a flexible timing engine.
Refer to the
Generation.
Simultaneous MIO X Series devices use AI Sample Clock
(ai/SampleClock) to perform simultaneous sampling on all active analog
channels. Since there is one ADC per channel, AI Sample Clock controls
the sample period on all the channels in the task.
An acquisition with posttrigger data allows you to view data that is acquired
after a trigger event is received. A typical posttrigger DAQ sequence is
shown in Figure 4-28. The sample counter is loaded with the specified
number of posttrigger samples, in this example, five. The value decrements
with each pulse on AI Sample Clock, until the value reaches zero and all
desired samples have been acquired.
An acquisition with pretrigger data allows you to view data that is acquired
before the trigger of interest, in addition to data acquired after the trigger.
Figure 4-29 shows a typical pretrigger DAQ sequence. The AI Start Trigger
signal (ai/StartTrigger) can be either a hardware or software signal. If
AI Start Trigger is set up to be a software start trigger, an output pulse
appears on the ai/StartTrigger line when the acquisition begins. When the
AI Start Trigger pulse occurs, the sample counter is loaded with the number
of pretrigger samples, in this example, four. The value decrements with
each pulse on AI Sample Clock, until the value reaches zero. The sample
X Series User Manual
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Clock Routing section of Chapter 9,
AI Start Trigger
AI Sample Clock
Sample Counter
Figure 4-28. Typical Posttriggered DAQ Sequence
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section.
Digital Routing and Clock
4 3 2 1 0
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