Table 4-3 Rsp Status Write Bits - Nintendo Ultra64 Programmer's Manual

RSP Coprocessor 0
86
The 'broke', 'single-step', and 'interrupt on break' bits are used by the
debugger.
The signal bits can be used for user-defined synchronization between the
CPU and the RSP.
On power-up, this register contains 0x0001.
When writing the RSP status register, the following bits are used.

Table 4-3 RSP Status Write Bits

bit
clear HALT.
0
(0x00000001)
set HALT.
1
(0x00000002)
clear BROKE.
2
(0x00000004)
clear RSP interrupt.
3
(0x00000008)
set RSP interrupt.
4
(0x00000010)
clear SINGLE STEP.
5
(0x00000020)
set SINGLE STEP.
6
(0x00000040)
clear INTERRUPT ON BREAK.
7
(0x00000080)
set INTERRUPT ON BREAK.
8
(0x00000100)
clear SIGNAL 0
9
(0x00000200)
Description