Su Is Bypassed; Figure 2-9 Pipeline Bypassing - Nintendo Ultra64 Programmer's Manual

RSP Architecture
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An obvious question is "why isn't the VU bypassed?" As illustrated in Figure 2-8, the final result of a vector
computation is not available until very late in the WB stage of the pipeline.
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Obviously, pipeline stalls should be avoided by the programmer (when
possible) for the best performance.
Because the SU is
registers for loads (and coprocessor moves) and VU registers.

SU is Bypassed

Bypassing
execution pipelines.
Instead of waiting for the result of a previous instruction to be written to its
destination register, a subsequent instruction can use the (correct) value
which is residing in a temporary register in the arithmetic and logical unit.
Figure 2-9
IF
add $4, $4, $5
add $3, $4, $6
add $7, $3, $8
sw $7, 0($10)
For software, this means that results from SU instructions are available in the
next clock cycle, removing the concern of preventing pipeline stalls.
bypassed
(see below), this section only applies to SU
forwarding
, or , is a technique commonly used to accelerate RISC
Pipeline Bypassing
RD EX DF WB
IF RD EX DF
IF RD EX
IF RD
WB
DF WB
EX DF WB
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