Mary Jo's Rules; Register Hazards - Nintendo Ultra64 Programmer's Manual

Mary Jo's Rules

Avoiding pipeline stalls in software can be accomplished by understanding
the following rules.
1.
2.
3.
4.
5.

Register Hazards

The RSP hardware implements register hazard locking for SU and VU
registers. Once an instruction is fetched and decoded, its destination register
is marked as a "hazard"; if this register is used as an input to a subsequent
instruction, the pipeline will stall.
1
Named after Mary Jo Doherty, the designer of the RSP.
Revision 1.0
1
VU register destination writes 4 cycles later (need 3 cycles between
load and use). This applies to vector computational instructions,
vector loads, and coprocessor 2 moves (mtc2).
SU register load takes 3 cycles (need 2 cycles between load and
use). This applies to SU loads and coprocessor moves (mfc0,
cfc2, mfc2). SU computational results are available in the next
cycle (see "SU is Bypassed" on page 44).
Any any
load followed by
bubble. Coprocessor moves (mtc0, mfc0, mtc2, mfc2,
ctc2, cfc2) count as both loads
A branch target not 64-bit aligned always single issues.
Branches:
a. Can dual issue (with preceding instruction).
b. No branch instruction permitted in a delay slot.
c. Delay slot always single issues.
d. Taken branch causes a 1 cycle bubble.
store 2 cycles later, causes a one cycle
and
stores.
Execution Pipeline
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