Figure 3-5 Transpose Loads And Stores - Nintendo Ultra64 Programmer's Manual

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Store Transpose, Element 5
Revision 1.0
dest_short[ Slice ] = source_short[((Slice +
A transpose is shown in Figure 3-5, with 8x8 block of 8 shorts in 8 VU
registers numbered in row order for the 64 elements of the block. The other
14 vector loads and stores needed for the transpose are similar. For a
memory-to-memory transpose, the instructions used are ltv and swv, and
for a register-to-register transpose, stv and ltv.
Interlock is performed by enabling the source and destination register
comparisons on only the upper two register number bits, that is, making any
interlock comparison to the 8 registers within a transpose block true.
Transpose Loads and Stores
Figure 3-5
VT
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128b memory word
VT+7
(Element >> 1)) & 0x7)]
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VU Loads and Stores
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Load Transpose, Element 3
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