Major R4000 Differences; Pipeline Depth; No Interrupts, Exceptions, Or Traps; Coprocessors - Nintendo Ultra64 Programmer's Manual

Major R4000 Differences

Revision 1.0
The MIPS R4000 series processors provide a convenient framework for
learning about the RSP.

Pipeline Depth

Pipeline depth varies among MIPS processors and their implementations.
The RSP has a pipeline depth of 5.

No Interrupts, Exceptions, or Traps

The RSP operates as a slave processor. There is no support for interrupts,
exceptions, or traps.

Coprocessors

The RSP implements the following MIPS Coprocessors:
• Coprocessor 0 (system control). The RSP coprocessor 0 is
compatible with the R4000 coprocessor 0. The RSP coprocessor 0 is
explained in Chapter 4, "RSP Coprocessor 0".
• Coprocessor 2 (VU) implements the vector unit.
Other MIPS coprocessors, including coprocessor 1 (floating point processor)
not
are implemented.

Missing Instructions

The following R4000 instructions are not present in the RSP instruction set:
•
LDL, LDR, LWL, LWR, LWU, SWL, SDL, SDR, SWR, LL, LLD,
LDC1, LDC2, LD, SDC1, SDC2, SD, (all 64-bit loads/stores, load
locked, and load/store left/right)
SC, SCD, (store conditionals)
•
Major R4000 Differences
not
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