Vu Loads And Stores; Figure 3-1 Vu Load And Store Instruction Format - Nintendo Ultra64 Programmer's Manual

Vector Unit Instructions

VU Loads and Stores

31
LWC2 or SWC2
48
Vector loads and stores are scalar unit (SU) instructions used to move the
contents of DMEM to and from VU registers (see "VU Register Format" on
page 34). VU loads and stores can only access DMEM; they cannot access
DRAM. Data must be transferred into DMEM using a DMA operation before
use.
VU Load and Store instructions follow the general format of MIPS
Coprocessor loads and stores (LWC2, SWC2), except for a different
interpretation of the 16 offset bits. This usage of the 16 bit offset field in MIPS
coprocessor opcode space extends the number of memory operations,
without using up a lot of instruction space.
Figure 3-1
26 25 21 20
base vt
The operands are:
Base
is an SU register containing a DMEM memory address. Only the
lower 12 bits of this register are used, other bits are ignored.
VT
is the VU register to or from which memory data is written.
opcode
The
Element
Offset
is a 7 bit constant shifted by the memory item size and added to
the memory address in
assembly language must be an operand-size-aligned integral; a
multiple of 2 bytes for a short load, 4 bytes for a long, etc. Since the
offset is added to the
byte-aligned, however.
All VU loads are
(results from a VU load are available for use in the fourth instruction
following the load). If a VU instruction attempts to use the destination
VU Load and Store Instruction Format
16 15 11
opcode
is the memory item type and operation being performed.
is the byte element of the VU register being accessed.
base . This means that the offset supplied in the
base
, the effective address can still be
delayed load instructions,
10 7 6
element offset
with three load delay slots
0