Execution Pipeline; Rsp Block Diagram - Nintendo Ultra64 Programmer's Manual

Execution Pipeline

Revision 1.0

RSP Block Diagram

The RSP execution pipeline is illustrated in Figure 2-8.
The scalar unit of the RSP has a five stage pipeline:
IF Instruction Fetch. During this stage, two instruction are
fetched and decoded, dual-issuing, if possible.
RD Register Access and Instruction Decode. Control is set
up for functional units based on instruction decode.
EX Execute. For computational operations, the result is
calculated; for loads/stores/branches, the address is
calculated.
DF Data Fetch. For loads, the data is fetched; store data is
stored.
WB Write Back. Results are written back to registers.
The vector unit also has a five stage pipeline:
IF Instruction Fetch. Nothing happens in the VU during
this stage.
RD Register Access and Instruction Decode. Muxing for
"scalar mode".
MUL Multiply. During this stage, computational operations
are computed. Reciprocal operations begin
table-lookup.
ACC Accumulate. Additional computation is performed.
Reciprocal operations perform table-lookup.
WB Write Back. Minor computations and writing of data to
vector registers.
Execution Pipeline
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