Revision 1.0
SU and VU Interaction
SU and VU Interaction
The RSP can execute two instructions per clock cycle, one scalar instruction
and one vector instruction. The scalar unit and vector unit operate in
parallel.
Dual Issue of Instructions
at most
The instruction fetch cycle can fetch
two instructions, one SU and
one VU. If there are no register conflicts, both instructions can be issued in
parallel.
Instructions are paired in order, they are not re-ordered to facilitate dual
issue. They do not need to be aligned as one SU and one VU in a 64-bit word.
If the pipeline stalls due to register conflicts (see "Register Hazards" on
no
page 43),
instructions are issued.
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