Interrupts, Exceptions, And Processor Status; Interrupts; Exceptions; Processor Status - Nintendo Ultra64 Programmer's Manual

RSP Architecture

Interrupts, Exceptions, and Processor Status

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Interrupts

The RSP does not respond to interrupts, and it can only generate a single
interrupt (MI_INTR_SP), triggered by the break instruction.

Exceptions

No RSP instruction can cause an exception, and there are no exception
handling facilities in the RSP.

Processor Status

The RSP has a processor status register in coprocessor 0, this register can be
used to communicate with the CPU. See page 85 for more information.