Normal - Nintendo Ultra64 Programmer's Manual

Vector Unit Instructions
Opcode
lfv, sfv
ltv, stv,
swv
50
Memory Item
4 8b every 4th,
unssigned (fourth pack)
8 16b (transpose, wrap)
If an illegal alignment (or element value) is attempted, something
loaded or stored, but probably not what was intended.

Normal

Normal loads and stores move a single memory item to or from an element
of a VU register. Items are
quad
bit), and
element is aligned to the size of the item.
Quad and rest operands update the portion of the memory item or VU
register which fall within the aligned quad word.
Quad operations move a byte-aligned quad word up to the 16 byte
boundary, that is, (address) to ((address & ~15) + 15) to/from VU register
element 0 to (address & 15).
Rest is used to move a byte-aligned quad word up to the byte address, that
is, (address & ~15) to (address - 1) to/from VU register element
(16 - (address & 15)) to 15. A rest with a byte address of zero writes no
bytes.
The quad and rest pair can then move a byte-aligned quad word to/from an
entire vector register in two instructions. (This can also be performed with
two byte-aligned double instructions, although quad and rest allow the two
quad words to be disjoint.) A quad word on a quad word boundary can be
moved in one quad instruction.
Memory VU Element
Alignment (legal values)
quad+0 to 3 0, 8
quad 0-14 by 2
byte
(8 bit),
rest
or (128 bit). The memory address is byte aligned. The VU
Offset Shift
Amount
<< 4
<< 4
short long
(16 bit), (32 bit),
will
be
double
(64