National Instruments 653 Series User Manual page 89

For traditional ni-daq. high-speed digital i/o devices for pci, pxi, compactpci, at, eisa, and pcmcia bus systems
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Chapter 3
Timing Diagrams
ACK
REQ
Input Data Valid
(REQ-edge
Latching)
Input Data Valid
(REQ-edge
Latching Disabled)
Parameter
Input Parameters
t
REQ pulse width
rr*
t
REQ inactive duration
r*r
t
ACK to next REQ
ar
t
Input data setup to REQ active
dir(1)
(with REQ-edge latching)
t
Input data hold from REQ active
rdi
(with REQ-edge latching)
t
Input data setup to REQ
dir(2)
(with REQ-edge latching disabled)
t
Input data hold from ACK
adi
(with REQ-edge latching disabled)
Output Parameters
t
ACK pulse width
aa*
t
REQ inactive to ACK inactive
r*a*
t
1
(min.) = 125 + programmable delay
aa*
Note
With REQ-edge latching enabled (default) REQ edge determines when data is
latched. Input data valid must be held before active-going REQ edge a minimum of t
With REQ edge disabled, it must be held t
occurs.
NI 653X User Manual
t
aa*
t
r*a*
t
ar
t
r*r
t
t
dir(1)
rdi
t
dir(2)
Description
Figure 3-34. Long-Pulse Input Timing Diagram
after the next active-going ACK signal edge
adi
3-34
t
rr*
ACK and REQ are shown as active high.
Minimum
75
75
0
0
10
0
0
1
125
150
t
adi
Maximum
ns.
rdi
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