National Instruments 653 Series User Manual page 115

Note This feature is not available on the NI PCI-6534.
10 MHz
RTSI and PXI Bus Triggers
Note If you configure a signal to be received from the RTSI bus, do not attach it to an
external source. Also, do not configure the NI 653X to generate that signal internally.
© National Instruments Corporation
The PLL circuitry consists of a voltage-controlled crystal oscillator
(VCXO) with a tuning range of ±50 ppm. The VCXO generates the
20 MHz master clock used onboard the NI PXI-6534.
The PLL locks to the 10 MHz system clock (PXI_CLK10) on the PXI
backplane bus. A phase comparator running at 1 MHz compares the PXI
bus and VCXO clock. The loop filter then processes the error signal and
outputs a control voltage for the VCXO. Refer to Figure D-6 for a block
diagram of the PLL circuit on the NI PXI-6534.
The PLL circuit is automatically enabled when the NI PXI-6534 is powered
on. No configuration steps are required in order to utilize PLL
synchronization.
Phase
Comparator
Div/10 +
–
Div/20
Figure D-6. PLL Circuit Block Diagram
The seven RTSI lines on the RTSI bus provide a flexible interconnection
scheme for any device sharing the RTSI or PXI trigger bus. Any control
signal on the device can connect to a RTSI or PXI trigger bus line. You can
drive output control signals onto the bus and receive input control signals
from the bus. Figure D-7 shows the signal connection scheme.
Appendix D
Loop
VCXO
Filter
D-11
Hardware Considerations
20 MHz Out
Synched to 10 MHZ
Backplane Clock
NI 653X User Manual