National Instruments 653 Series User Manual page 140

Index
input timing diagram (figure), 3-34
output handshaking sequence
(figure), 3-35
output state machine (figure), 3-35
output timing diagram (figure), 3-36
polarity for handshaking I/O
comparison of handshaking protocols
(table), 3-4
controlling line polarity, 2-23
selecting polarity, 2-19
start and stop trigger
change detection, 2-31
pattern I/O, 2-9
start trigger
change detection, 2-30
pattern I/O, 2-8
trailing-edge protocol
input handshaking sequence
(figure), 3-22
input state machine (figure), 3-23
input timing diagram (figure), 3-24
output handshaking sequence
(figure), 3-25
output state machine (figure), 3-25
output timing diagram (figure), 3-26
applications, choosing correct mode for
(table), 2-1
asynchronous handshaking protocol, 3-11
AT-DIO-32HS
benchmark results (table), E-4
block diagram, D-1
installation, 1-8
support for DMA transfers (table), E-3
B
benchmark results. See optimizing transfer
rates
block diagrams
AT-DIO-32HS, D-1
DAQCard-6533 for PCMCIA, D-2
NI 653X User Manual
PCI/PXI-6534, D-4
PCI-DIO-32HS, PCI/PXI-7030/6533, and
PXI-6533, D-3
phase-locked loop circuit (figure), D-11
burst handshaking protocol
comparison of protocols (table), 3-4
input timing diagram
default timing diagram (figure), 3-7
PCLK reversed (figure), 3-9
transfer example (figure), 3-6
maximum transfer rate (table), E-2
output timing diagram
default timing diagram (figure), 3-8
PCLK reversed (figure), 3-10
transfer example (figure), 3-6
overview, 2-18
PCLK signal direction, 2-18
bus
interface specifications, A-3
RTSI
overview, 1-1
RTSI and PXI trigger bus
interfaces, D-10
C
cable selection and termination
Schottky-diode termination scheme, D-7
transmission line termination
(figure), D-8
calibration certificate (NI resources), F-2
change detection
connecting signals, 2-33
continuous or finite data transfer
continuous input, 2-32
DMA or interrupt transfers, 2-33
finite, 2-32
overview, 2-28
port and timing controller combinations
(table), 2-28
I-2 ni.com