Chapter 3
Timing Diagrams
PCLK
ACK
REQ
Data Out Valid
Parameter
Input Parameters
t
PCLK cycle time
pc
t
PCLK high pulse duration
pw
t
PCLK low pulse duration
pl
t
Setup time from REQ valid to PCLK
rs
falling edge
t
Hold time from PCLK to REQ invalid
rh
Output Parameters
t
PCLK to ACK valid
pa
t
Hold time from PCLK to ACK invalid
ah
t
PCLK to output data valid
pdo
t
Hold time from PCLK to output data
doh
invalid
All timing values are in nanoseconds.
NI 653X User Manual
t
pw
t
pa
t
rs
t
pdo
Description
Figure 3-6. Burst Output Timing Diagram (Default)
t
pc
t
pl
3-8
t
ah
t
rh
t
doh
Minimum
Maximum
50
20
20
1
0
—
3
—
5
—
—
—
—
—
22
—
28
—
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