National Instruments 653 Series User Manual page 79

For traditional ni-daq. high-speed digital i/o devices for pci, pxi, compactpci, at, eisa, and pcmcia bus systems
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Chapter 3
Timing Diagrams
ACK
REQ
Input Data Valid
(REQ-edge
Latching)
Input Data Valid
(REQ-edge
Latching Disabled)
Parameter
Input Parameters
t
REQ pulse width
rr*
t
REQ inactive duration
r*r
t
Input data setup to REQ inactive
dir*
(with REQ-edge latching)
t
Input data hold from REQ inactive
r*di
(with REQ-edge latching)
t
Input data setup to REQ
dir
(with REQ-edge latching disabled)
t
Input data hold from ACK
adi
(with REQ-edge latching disabled)
Output Parameters
t
ACK pulse width
aa*
t
ACK inactive to next REQ inactive
a*r*
1
t
(min.) = 225 + programmable delay
aa*
2
t
(max) = 275 + programmable delay
aa*
Note
When REQ-edge latching is enabled (default), the REQ edge determines when data
will be latched. Input data valid must be held t
When REQ-edge latching is disabled, input data valid needs to be held t
active-going edge of the ACK signal occurs.
NI 653X User Manual
t
r*r
t
r*di
t
dir*
Description
Figure 3-22. Trailing-Edge Input Timing Diagram
t
t
aa*
a*r*
t
rr*
t
dir
ACK and REQ are shown as active high.
after the trailing edge of REQ occurs.
r*di
3-24
Minimum
Maximum
75
75
0
10
0
0
1
225
275
0
after the
adi
t
adi
2
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