National Instruments 653 Series User Manual page 114

Appendix D Hardware Considerations
RTSI and PXI Trigger Bus Interfaces
Board, RTSI, and PXI Bus Clocks
Phase-Locked Loop Circuit (NI PXI-6534 Only)
NI 653X User Manual
You can use the seven bidirectional RTSI lines on the RTSI bus to share
signals between devices. Use the RTSI bus interface to synchronize
multiple cards or change control signals with multiple devices.
The NI PCI-6534, NI PCI-DIO-32HS and NI AT-DIO-32HS each contain
a RTSI connector and an interface to the National Instruments RTSI bus.
The RTSI bus provides seven trigger lines and a system clock line. All NI
AT- and PCI-bus devices that have RTSI bus connectors can be cabled
together inside a computer to share these signals.
The NI PXI-653X uses pins on the PXI J2 connector to connect the RTSI
bus to the PXI trigger bus as defined in the PXI Specification, rev. 1.0. All
NI PXI modules that provide a connection to these pins can be connected
with software. This feature is available only when the NI PXI-653X is used
in a PXI-compatible chassis. It is not supported in CompactPCI chassis.
The NI 653X requires a clock to run the handshaking logic and to generate
sampling intervals for pattern I/O. The frequency timebase must be
20 MHz.
The NI 653X can use its internal 20 MHz clock source, or you can provide
a clock from another 20 MHz device over the RTSI bus. When using its
internal 20 MHz clock, the NI 653X can also drive its internal timebase
onto the bus and to another device that uses a 20 MHz clock.
Whether internal or external, the 20 MHz clock serves as the primary
frequency source for the NI 653X. By default, the NI 653X uses an internal
clock. You can programmatically change the source of the clock through
software.
♦
NI PXI-653X—The NI PXI-653X uses PXI trigger line 7 as the RTSI clock
line.
A phase-locked loop (PLL) circuit accomplishes the synchronization of
multiple NI PXI-6534 devices or other PXI devices which support PLL
synchronization by allowing these devices to all lock to the same reference
clock present on the PXI backplane. This circuit allows you to trigger input
or output operations on different devices and ensures that samples occur at
the same time.
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