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MDIO Implementation in the EMAC
The EMAC implements an STA (MDIO master), controlled through the host interface,
which can be connected to one or more MMDs (PHY devices) to access their management
registers.
The PCS/PMA sublayer of the EMAC, used for 1000BASE-X or SGMII, also contains an
MMD (MDIO slave). The physical address of this MMD is set via the
PHYEMAC#PHYAD[4:0] port of the EMAC. However, the PCS/PMA sublayer also
responds to a PHYAD of zero.
Example Use Models
Figure 3-49
master to access the configuration registers of an external PHY.
EMAC#
Host
Interface
PHYEMAC#MDIN, EMAC#PHYMDOUT, and EMAC#PHYMDTRI must be connected to
a 3-state buffer to create the bidirectional wire, MDIO. This 3-state buffer can be either
external to the FPGA or internally integrated by using an IOBUF with an appropriate I/O
standard for the external PHY as illustrated in
To obtain this functionality whenever the host interface is used, the EMAC's Management
Data Input/Output (MDIO) Interface signals are wired as shown in
TIEEMAC#CONFIGVEC[73] (MDIO enable) tied High.
This example intentionally does not use the PCS/PMA sublayer (a GMII or RGMII
physical interface can be selected, or the PCS/PMA sublayer can be configured only
through its tie-off vectors, TIEEMAC#CONFIGVEC[78:74]). However, it is still internally
connected to the MDIO and replies to a read or write transaction, if addressed. The
PHYAD of the PCS/PMA sublayer must not be addressed.
www.BDTIC.com/XILINX
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
illustrates a user case example, where the Host Interface is used as the MDIO
Address Filter Registers
MDIO Interface
(STA MDIO Master)
Configuration Registers
Figure 3-49: User Case 1: MDIO Access to External PHY
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PCS/PMA
Sublayer
(MMD
MDIO Slave)
PHYEMAC#MCLKIN
GND
EMAC#PHYMCLKOUT
MDIO
PHYEMAC#MDIN
Arbitration
EMAC#PHYMDOUT
EMAC#PHYMDTRI
Figure
3-49.
MDIO Interface
OBUF
MDC
OPAD
I
O
Connect to
IOBUF
external PHY
(MMD
O
MDIO Slave)
IOPAD
MDIO
I
IO
T
UG074_3_74_112705
Figure 3-49
with
95
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