Xilinx Virtex-4 User Manual page 69

R
The block diagram for the receiver statistics MUX in the Ethernet MAC is shown in
Figure
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Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
3-36.
RX_STATISTICS_VECTOR[26:0]
CLIENTEMAC#RXCLIENTCLKIN
EMAC#CLIENTRXSTATSBYTEVLD
EMAC#CLIENTRXSTATS[6:0]
CLIENTEMAC#RXCLIENTCLKIN
CLIENTEMAC#RXCLIENTCLKIN
Figure 3-36: Receiver Statistics MUX Block Diagram
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Ethernet MAC
(Internal Signal)
[26:0]
RXSTATSMUX
RXSTATSDEMUX
RESET
RXSTATSVEC[26:0]
User Defined
Statistics Processing Block
Client Interface
RX_STATISTICS_VALID
(Internal Signal)
Ethernet MAC Block
FPGA Fabric
EMAC#CLIENTRXSTATSVLD
RXSTATSVLD
ug074_3_38_080805
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