Gmii Signals - Xilinx Virtex-4 User Manual

Chapter 4: Physical Interface
Double data rate input and output registers are used to achieve the 25 MHz and 2.5 MHz
4-bit data rate at speeds below 1 Gb/s, resulting in a scheme that utilizes two clock buffers
less than
scheme does not operate in half-duplex mode. In addition, alignment logic must be
provided on the receiver side to align the start of frame delimiter in the 8-bit data input to
the EMAC.
GTX_CLK must be provided to the Ethernet MAC with a high-quality 125 MHz clock that
satisfies the IEEE Std 802.3-2002 requirements.
The CLIENTEMAC#TXGMIIMIICLKIN and CLIENTEMAC#TXCLIENTCLKIN ports are
supplied by the output of a BUFGMUX. At 1 Gb/s, the BUFGMUX routes through the
EMAC#CLIENTTXCLIENTCLKOUT signal. At 100 Mb/s and 10 Mb/s, the BUFGMUX is
switched to supply tx_clk_div2 to the EMAC. This signal is the MII_TX_CLK_# input
divided by two in frequency. The output of the BUFGMUX also clocks all the transmit
client and GMII logic.
A DCM must be used on the GMII_RX_CLK_# clock path as illustrated in
meet the GMII input setup and hold requirements when operating at 1 Gb/s. Phase
shifting may then be applied to the DCM to fine tune the setup and hold times of the input
GMII receiver signals which are sampled at the GMII IOB input flip-flops.
When operating at 10 Mb/s and 100 Mb/s, the DCM is bypassed and held in reset. This is
achieved using the BUFGMUX global clock multiplexer shown in
requirement to bypass the DCM because the clock frequency of GMII_RX_CLK_# is
2.5 MHz when operating at 10 Mb/s and 2.5 MHz is below the DCM low frequency
threshold for Virtex-4 FPGAs. However, at the 10 Mb/s and 100 Mb/s operating speeds,
input setup and hold margins increase appropriately and the input MII data can be
sampled correctly without use of the DCM.
At 1 Gb/s, the second BUFGMUX supplies the DCM phase-shifted GMII_RX_CLK_# to
the PHYEMAC#RXCLK and CLIENTEMAC#RXCLIENTCLKIN ports. At 100 Mb/s and
10 Mb/s, the BUFGMUX is switched to provide rx_clk_div2 to the EMAC. This clock is the
GMII_RX_CLK_# input divided by two in frequency. The output of the BUFGMUX also
clocks all the receiver client and GMII logic. The CLIENTEMAC#DCMLOCKED port must
be tied High.

GMII Signals

An Ethernet MAC wrapper has all necessary pin connections to configure the primitive
into GMII.
Table 4-2: GMII Interface Signals
Signal
GTX_CLK
GMII_TXD[7:0]_#
GMII_TX_EN_#
GMII_TX_ER_#
GMII_TX_CLK_#
GMII_CRS_#
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112
Figure 4-9. However, because the EMAC is kept in 1 Gb/s mode at all speeds, the
Table 4-2 describes the GMII interface signals.
Direction
The transmit clock at 125 MHz. The clock timing and other characteristics meet
Input the IEEE Std 802.3-2002 specification. Other transmit clocks are derived from this
clock.
Output Transmits data to PHY.
Output Transmits data enable to PHY.
Output Transmits error signal to PHY.
Output Transmits clock out to PHY.
Input Carrier sense control signal from PHY, only if tri-mode is selected.
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Figure
Description
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
R
Figure 4-10 to
4-10. It is a