Xilinx Virtex-4 User Manual page 100

Fpga embedded tri-mode ethernet mac
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Chapter 4: Physical Interface
CLIENTEMAC#DCMLOCKED
EMAC#CLIENTRXCLIENTCLKOUT
CLIENTEMAC#RXCLIENTCLKIN
EMAC#CLIENTRXD[15:0]
EMAC#CLIENTRXDVLD
EMAC#CLIENTRXDVLDMSW
EMAC#CLIENTRXGOODFRAME
EMAC#CLIENTRXBADFRAME
EMAC#CLIENTRXFRAMEDROP
EMAC#CLIENTRXDVREG6
EMAC#CLIENTRXSTATS[6:0]
EMAC#CLIENTRXSTATSBYTEVLD
EMAC#CLIENTRXSTATSVLD
EMAC#CLIENTTXCLIENTCLKOUT
CLIENTEMAC#TXCLIENTCLKIN
CLIENTEMAC#TXD[15:0]
CLIENTEMAC#TXDVLD
CLIENTEMAC#TXDVLDMSW
EMAC#CLIENTTXACK
CLIENTEMAC#TXUNDERRUN
EMAC#CLIENTTXCOLLISION
EMAC#CLIENTTXRETRANSMIT
CLIENTEMAC#TXIFGDELAY[7:0]
CLIENTEMAC#TXFIRSTBYTE
EMAC#CLIENTTXSTATS
EMAC#CLIENTTXSTATSBYTEVLD
EMAC#CLIENTTXSTATSVLD
CLIENTEMAC#PAUSEREQ
CLIENTEMAC#PAUSEVAL[15:0]
HOSTADDR[9:0]
HOSTMIIMSEL
HOSTOPCODE[1:0]
HOSTMIIMRDY
HOSTRDDATA[31:0]
HOSTWRDATA[31:0]
HOSTEMAC1SEL
DCREMACENABLE
EMACDCRACK
EMACDCRDBUS[0:31]
DCREMACABUS[8:9]
DCREMACCLK
DCREMACDBUS[0:31]
DCREMACREAD
DCREMACWRITE
DCRHOSTDONEIR
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100
MII
Ethernet
MAC
HOSTCLK
HOSTREQ
Figure 4-1: Ethernet MAC Configured in MII Mode
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WRAPPER
VHDL/Verilog
MII_RX_CLK_#
MII_RXD[3:0]_#
MII_RX_DV_#
MII_RX_ER_#
MII_TX_CLK_#
MII_TXD[3:0]_#
MII_TX_EN_#
MII_TX_ER_#
MII_COL_#
MII_CRS_#
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
R
RESET
UG074_3_50_022007

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