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1000BASE-X PCS/PMA
The full-duplex PCS with PMA interface for 1000BASE-X is defined in IEEE Std 802.3-2002,
Clauses 36 and 37.
Figure 4-25
of the PCS and PMA sublayers can replace the GMII interface. The functional blocks of the
PCS and PMA sublayers are:
•
•
•
•
•
The management register block in the PCS sublayer is accessed through the MDIO
interface as though there is an externally connected PHY. This block is used to configure
the operation of the PCS sublayer, the PMA sublayer, and auto-negotiation. The host
interface can control the MDIO interface as defined in
When the management interface is not present, the PCS sublayer management register
block must be accessed using a separate MDIO controller outside the Ethernet MAC.
The MGT provides some of the PCS layer functionality including 8B/10B encoding and
decoding, and serialization and deserialization in the PMA layer.
1000BASE-X PCS/PMA Interface
Figure 4-26
physical interface. The client interfaces can be either 8 bits or 16 bits wide. In 16-bit client
mode, the Ethernet MAC can operate at 250 MHz, enabling a 2.5 Gb/s line rate. In this
interface, not all the ports of the Ethernet MAC are used.
www.BDTIC.com/XILINX
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
shows a block diagram of the PCS and PMA sublayers. The functional blocks
Transmit engine
Auto-negotiation block
Receive engine and synchronization block
PCS management register block
RocketIO transceiver
MAC TX
Interface
MAC RX
Interface
MDIO
Interface
Figure 4-25: Ethernet PCS/PMA Sublayer Extension
shows the Ethernet MAC configured with 1000BASE-X PCS/PMA as the
www.xilinx.com
PCS Transmit
Engine
Auto-negotiation
PCS Receive
Engine &
Synchronization
PCS
Management
"MDIO Interface" in Chapter
1000BASE-X PCS/PMA
TXP/TXN
RXP/RXN
UG074_3_62_012508
3.
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