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Chapter 3: Client, Host, and MDIO Interfaces
Table 3-6: Management Interface Transaction Types
Host Clock Frequency
The host clock (HOSTCLK) is used to derive the MDIO clock, MDC, and is subject to the
same frequency restrictions. See the
parameters.
Configuration Registers
The Ethernet MAC has seven configuration registers. These registers are accessed through
the host interface and can be written to at any time. Both the receiver and transmitter logic
only respond to configuration changes during IFGs. The configurable resets are the only
exception, because the reset is immediate.
Configuration of the Ethernet MAC is performed through a register bank accessed through
the Host interface. Any time an address shown in
write is performed from the same configuration word, with the exception of the read-only
Ethernet MAC mode configuration register and the RGMII/SGMII configuration register.
Only the speed selection is both readable and writable in the Ethernet MAC mode
configuration register.
Table 3-7: Configuration Registers
Notes:
1. HOSTEMAC1SEL acts as bit 10 of HOSTADDR.
The configuration registers and the contents of the registers are shown in
Table
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74
Transaction
Configuration/Address Filter
MDIO access
{HOSTEMAC1SEL, HOST_ADDR[9:0]}
0x200
0x240
0x280
0x2C0
0x300
0x320
0x340
3-14.
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HOSTMIIMSEL
0
1
Virtex-4 FPGA Data Sheet
for the HOSTCLK frequency
Table 3-7
is accessed, a 32-bit read or
Register Description
Receiver Configuration (Word 0)
Receiver Configuration (Word 1)
Transmitter Configuration
Flow Control Configuration
Ethernet MAC Mode Configuration
RGMII/SGMII Configuration
Management Configuration
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
R
HOSTADDR[9]
1
X
Table 3-8
through
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