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Chapter 4: Physical Interface
Management Registers
SGMII has a similar PCS sublayer managed register block defined in IEEE Std 802.3-2002
Clause 37. This set of 10 management registers, accessed through MDIO, is described in the
1000BASE-X PCS/PMA section
negotiation Advertisement Register (register 4) and the auto-negotiation Link Partner
Ability BASE Register (register 5) are different in the SGMII specification.
Table 4-8
Table 4-7: SGMII Auto-Negotiation Advertisement Register (Register 4)
Bit(s)
Name
All bits
4.15:0
Table 4-8:
SGMII Auto-Negotiation Link Partner Ability Base Register (Register 5)
Bit(s)
Name
5.15
Link up/down
5.14
Acknowledge
5.13
Reserved
5.12
Duplex mode
5.11:10
Speed
5.9:1
Reserved
5.0
Reserved
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134
describe these two registers with regard to the SGMII specification.
Description
SGMII defined value sent from the MAC
to the PHY.
Description
1 = Link up.
0 = Link down.
Used by the auto-negotiation function to
indicate reception of a link partner's
base or next page.
Always return 0.
1 = Full Duplex.
0 = Half Duplex.
00 = 10 Mb/s.
01 = 100 Mb/s.
10 = 1000 Mb/s.
11 = Reserved.
Always returns 0s.
Always returns 1.
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("Management Registers," page
Attributes
Read Only
Attributes
Read only
Read only
Returns 0
Read only
Read only
Returns 0s
Returns 1
Embedded Tri-Mode Ethernet MAC User Guide
140). However, the auto-
Table 4-7
and
Default Value
000000000000001
Default Value
1
0
0
00
00
000000000
1
UG074 (v2.2) February 22, 2010
R
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