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Chapter 4: Physical Interface
RGMII Signals
An Ethernet MAC wrapper has all necessary pin connections to configure the primitive
into RGMII.
Table 4-3: 10/100/1000 RGMII Interface Signals
Signal
GTX_CLK
RGMII_TXC_#
RGMII_TXD_#
(1)
RGMII_TX_CTL_#
RGMII_RXC_#
RGMII_RXD_#
(1)
RGMII_RX_CTL_#
Notes:
1. See the Hewlett Packard RGMII specification v1.3 or v2.0 (section 3.4) for more information.
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122
Table 4-3
describes the 10/100/1000 RGMII interface signals.
Direction
The transmit clock at 125 MHz. The clock timing and characteristics
Input
meet the IEEE Std 802.3-2002 specification. Other transmit clocks are
derived from this clock.
Output
Transmits clock out to the PHY.
Transmits the first 4 bits of packet data ([3:0]) on the rising edge of
Output
RGMII_TXC_#, and the top 4 bits ([7:4]) on the falling edge. TXD is 4 bits
wide connecting to the PHY.
This signal is TXEN on the rising edge of RGMII_TXC_#, and an
Output
encoded TXERR on the falling edge.
Recovered clock from data stream by the PHY: 125 MHz, 25 MHz or
Input
2.5 MHz.
Receives the lower 4 bits of packet data ([3:0]) on the rising edge, and the
Input
upper 4 bits of packet data ([7:4]) on the falling edge of RGMII_RXC_#.
This signal is RXDV on the rising edge of RGMII_RXC_#, and an
Input
encoded RXERR on the falling edge.
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Description
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
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