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Chapter 4: Physical Interface
To ensure that the Ethernet MAC does not operate until the MGT has achieved all
necessary locks, the CLIENTEMAC#DCMLOCKED input signal to the EMAC# block is
generated using the TXLOCK and RXLOCK signals from the MGT, and the DCM
LOCKED output. Refer to the CORE Generator Ethernet MAC wrapper for the actual
implementation of this combined lock signal.
The EMAC#CLIENTRXCLIENTCLKOUT output port must be connected to a BUFG to
drive the receive client logic in the FPGA fabric, and then is routed back into the input
ports CLIENTEMAC#RXCLIENTCLKIN and CLIENTEMAC#TXCLIENTCLKIN. This
clock is also used for the transmit client logic.
SGMII Signals
An Ethernet MAC wrapper has all necessary pin connections to configure the primitive
into SGMII.
Table 4-6: 10/100/1000 SGMII and 1000BASE-X PCS/PMA Interface Signals
Signal
ENCOMMAALIGN_#
LOOPBACKMSB_#
MGTRXRESET_#
MGTTXRESET_#
POWERDOWN_#
SYNC_ACQ_STATUS_#
TXCHARDISPMODE_#
TXCHARDISPVAL_#
TXCHARISK_#
PHYAD[4:0]_#
RXBUFSTATUS[1:0]_#
RXCHARISCOMMA_#
RXCHARISK_#
RXCHECKINGCRC_#
RXBUFERR_#
RXCOMMADET_#
RXDISPERR_#
RXLOSSOFSYNC[1:0]_#
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132
Table 4-6
describes the 10/100/1000 SGMII interface signals.
Direction
Output
Enable PMA layer (MGT) to realign to commas.
Output
Loopback tests within the MGTs.
Output
Reset to receive PCS of MGT.
Output
Reset to transmit PCS of MGT.
Output
Power down the MGTs.
The output from the receiver's synchronization state machine of IEEE
Std 802.3, Clause 36.
When asserted High, synchronization on the received bitstream is
Output
obtained. The state machine is in one of the SYNC_AQUIRED states of
IEEE Std 802.3 Figure 36-9.
When deasserted Low, synchronization is not yet obtained.
Output
Set running disparity for current byte.
Output
Set running disparity value.
Output
K character transmitted in TXDATA.
Input
PHY address of MDIO register set for the PCS sublayer.
Receiver elastic buffer status: Bit [1] asserted indicates over flow or
Input
underflow.
Input
Comma detected in RXDATA.
K character received or extra data bit in RXDATA. Becomes the 10th bit
Input
in RXDATA when RXNOTINTABLE is asserted.
Input
Reserved, tie to GND.
Input
Reserved, tie to GND.
Input
Reserved, tie to GND.
Input
Disparity error in RXDATA.
Input
Reserved, tie to GND.
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Description
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
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