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Chapter 3: Client, Host, and MDIO Interfaces
Table 3-13: RGMII/SGMII Configuration Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
SGMII
LINK
0x320
SPEED
Bit
RGMII link: Valid in RGMII mode configuration only. When this
bit is 1, the link is up. When this bit is 0, the link is down. This
[0]
displays the link information from PHY to Ethernet MAC,
encoded by GMII_RX_DV and GMII_RX_ER during the IFG.
RGMII half-duplex mode: Valid in RGMII mode configuration
only. This bit is 0 for half-duplex mode and 1 for full-duplex
[1]
mode. This displays the duplex information from PHY to
Ethernet MAC, encoded by GMII_RX_DV and GMII_RX_ER
during the IFG.
RGMII speed: Valid in RGMII mode configuration only. Link
information from PHY to Ethernet MAC as encoded by
GMII_RX_DV and GMII_RX_ER during the IFG. This 2-bit
vector is defined with the following values:
[3:2]
10 = 1000 Mb/s
01 = 100 Mb/s
00 = 10 Mb/s
11 = N/A
[29:4]
Reserved
SGMII speed: Valid in SGMII mode configuration only. This
displays the SGMII speed information, as received by
TX_CONFIG_REG[11:10] in the PCS/PMA register. See
Table 4-8, page
134. This 2-bit vector is defined with the
following values:
[31:30]
10 = 1000 Mb/s
01 = 100 Mb/s
00 = 10 Mb/s
11 = N/A
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78
RESERVED
Description
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8
7
6
5
Default Value
0
0
All 0s
–
All 0s
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
R
4
3
2
1
0
RGMII
LINK
SPEED
R/W
R
R
R
R
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