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R
PCS/PMA mode, EMAC#CLIENTTXGMIIMIICLKOUT is derived from the
PHYEMAC#GTXCLK. See
Receive Clocking Scheme
Figure 5-2
RX_CORE_CLK and RX_GMII_MII_CLK are internal clock signals.
Ethernet MAC Block
BUFG
EMAC#CLIENTRXCLIENTCLKOUT
Client
Logic
CLIENTEMAC#RXCLIENTCLKIN
RX
Client
Datapath
The clock generation module takes the PHYEMAC#RXCLK from the physical interface
and generates the EMAC#CLIENTRXCLIENTCLKOUT to run the circuitry in the FPGA
fabric connecting to the client side. CLIENTEMAC#RXCLIENTCLKIN runs the client logic
and receive engine inside the Ethernet MAC. This clock signal must be from the FPGA
clock drivers (BUFG) of EMAC#CLIENTRXCLIENTCLKOUT.
When configured in MII/GMII/RGMII mode, the internal RX_GMII_MII_CLK is derived
from the PHYEMAC#RXCLK and used to run the MII/GMII/RGMII sublayer. When the
Ethernet MAC is configured in either SGMII or 1000BASE-X PCS/PMA mode, the clock to
run the PCS/PMA sublayer is generated from the PHYEMAC#GTXCLK. See
"Physical Interface"
Ethernet MAC Configuration
The Ethernet MAC can be configured using hardware or by accessing the registers through
the host interface in software. The three methods for configuration are described in the
following sections:
1.
2.
3.
Table 5-6
www.BDTIC.com/XILINX
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 4, "Physical Interface"
shows the clocks used in the receive module of the Ethernet MAC. In this figure,
PHYEMAC#GTXCLK
CLKGEN
RX_CORE_CLK
RX
Core
Figure 5-2: Receive Clocks
for clock usage.
Tie-off pins in hardware (see
Generic host bus using the host interface (see
DCR using the host interface (see
shows the register addresses for each of the two Ethernet MACs.
www.xilinx.com
PHYEMAC#RXCLK
RX_GMII_MII_CLK
PCS/PMA
"Tie-Off Pins" in Chapter
"Generic Host Bus" in Chapter
"Using the DCR Bus as the Host Bus" in Chapter
Ethernet MAC Configuration
for clock usage.
BUFG
RXCLK
from PHY
GMII/MII
Logic
ug074_3_02_102004
Chapter 4,
2)
3)
3)
149
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