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10/100/1000 SGMII Clock Management
Figure 4-24
1.25 Gb/s or below, oversampling is used by the built-in MGT digital receiver to recover
clock and data. Chapter 3 of UG076, Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide
provides more details about the digital receiver oversampling operation. The inputs of the
GT11CLK_MGT primitive connect to an external, high-quality reference clock with a
frequency of 250 MHz specifically for the MGT. The output SYNCLK1OUT connects to the
PLL reference clock input REFCLK1. TXOUTCLK1 is derived from the transmitter PLL.
TXOUTCLK1 feeds TXUSRCLK2 and the PHYEMAC#GTXCLK. RXRECCLK1 feeds a
BUFR that is used to clock the internal elastic buffer. This buffer is only necessary for
SGMII. The output of the BUFR also drives RXUSRCLK2. RXUSRCLK and TXUSRCLK are
both tied to ground.
FPGA Fabric RX Elastic
PHYEMAC#GTXCLK
www.BDTIC.com/XILINX
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
10/100/1000 Serial Gigabit Media Independent Interface (SGMII)
shows the clock management used with the SGMII interface. At a line rate of
250 MHz
Buffer
EMAC#
CLIENTEMAC#TXCLIENTCLKIN
EMAC#CLIENTTXCLIENTCLKOUT
CLIENTEMAC#RXCLIENTCLKIN
EMAC#CLIENTRXCLIENTCLKOUT
Figure 4-24: SGMII Clock Management
www.xilinx.com
MGTCLKP
MGTCLKN
GT11CLK_MGT
REFCLK1
BUFR
RXRECCLK1
RXUSRCLK2
'0'
RXUSRCLK
BUFG
TXOUTCLK1
TXUSRCLK2
'0'
TXUSRCLK
BUFG
X
SYNCLK1OUT
GT11
Client
Logic
UG074_3_61_070607
131
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