Xilinx Virtex-4 User Manual page 84

Chapter 3: Client, Host, and MDIO Interfaces
The DCR bridge ignores any new DCR command for host access until the current host
access is complete. Therefore, it is essential to determine when the host access is complete
before issuing a new DCR command.
Table 3-21
[9:2] in the DCR address space. UG018, PowerPC 405 Processor Block Reference Guide
describes the DCR operation.
Table 3-21: Ethernet MAC Host Interface Device Control Register Addresses
Notes:
1. This register is Read Only.
The four registers and the contents of the registers are shown in
Table
Table 3-22: DCR Data Register dataRegMSW
DCR
Offset
0 1 2 3 4
0xC
Bit
Data – Data input from the DCR bus for the Ethernet MAC registers is written into this
[31:0] register, and the most significant word of data is read out from the Ethernet MAC registers
and deposited into this register.
Table 3-23: DCR Data Register dataRegLSW
DCR
Offset
0 1 2 3 4
0xD
Bit
Data – Data input from the DCR bus for the Ethernet MAC registers is written into this
[0:31] register, and the least significant word of data is read out from the Ethernet MAC registers
and deposited into this register.
www.BDTIC.com/XILINX
84
shows the DCR addresses for the DCRs. The user assigns the DCR address bits
DCR Address
dataRegMSW
**_****_1100
dataRegLSW
**_****_1101
cntlReg
**_****_1110
RDYstatus
**_****_1111
3-25. DCR registers are big endian.
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Description
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Description
www.xilinx.com
DCR Name Register Width
dataRegMSW
dataRegLSW
Embedded Tri-Mode Ethernet MAC User Guide
R/W
32 bits R/W
32 bits R/W
32 bits R/W
(1)
32 bits R
Table 3-22 through
Default Value
Undefined
Default Value
Undefined
UG074 (v2.2) February 22, 2010
R