Using The Dcr Bus As The Host Bus - Xilinx Virtex-4 User Manual

R
Figure 3-43
four multicast address registers.
For reading a multicast address register in HOSTWRDATA[31:0], the RNW field is set to 1,
and the multicast address field should be set with the register number to be read. The
multicast address register read data is returned in HOSTRDDATA[31:0]. The LSW is the
multicast address [31:0]. The MSW contains 0x0000 and the multicast address [47:32]. For
examples of accessing a multicast address register, see
in Chapter
HOSTMIIMSEL acts as a read enable. It must be held Low for an even number of clock
cycles during a read operation.

Using the DCR Bus as the Host Bus

When the DCR bus is used to access the internal registers of the Ethernet MAC, the DCR
bus bridge in the host interface translates commands carried over the DCR bus into
Ethernet MAC host bus signals. These signals are then input into one of the Ethernet
MACs.
The DCR bus bridge contains four device control registers. The first two are used as data
registers, each is 32 bits wide (dataRegMSW and dataRegLSW). The third is used as a
control register (cntlReg).
The fourth device control register is used as a ready status register (RDYstatus). The
PowerPC 405 processor polls this register to determine access completion status. The bits
in this register are asserted when there is no access in progress. When an access is in
progress, a bit corresponding to the type of access is automatically deasserted. The bit is
automatically reasserted when the access is complete. Alternatively, the host interface can
also provide an interrupt request to inform the host of access completion. The user can
select either the polling or the interrupt method to inform the host of access status.
www.BDTIC.com/XILINX
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
shows the timing diagram for reading the multicast address from one of the
6.
HOSTCLK
HOSTMIIMSEL
HOSTOPCODE[1]
HOSTADDR[9:0]
HOSTWRDATA[31:0]
HOSTRDDATA[31:0]
Figure 3-43: Address Filter Multicast Address Register Read
www.xilinx.com
"Interfacing to the Processor DCR"
0x38C
LSW MSW
UG074_3_45_080805
Host Interface
83