Mii Signals - Xilinx Virtex-4 User Manual

Chapter 4: Physical Interface
EMAC#CLIENTTXGMIIMIICLKOUT
PHYEMAC#RXCLK
Clock Enable
EMAC#PHYTXD
PHYEMAC#RXD
CLIENTEMAC#TXCLIENTCLKIN
CLIENTEMAC#RXCLIENTCLKIN
EMAC#CLIENTTXACK
Registered
EMAC#CLIENTTXACK
Data (with registered ACK)

MII Signals

An Ethernet MAC wrapper has all necessary pin connections to configure the primitive
into the media independent interface.
Table 4-1: MII Interface Signals
Signal
MII_TXD[3:0]_#
MII_TX_EN_#
MII_TX_ER_#
MII_TX_CLK_#
MII_CRS_#
MII_COL_#
MII_RX_CLK_#
MII_RXD[3:0]_#
MII_RX_DV_#
MII_RX_ER_#
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104
Figure 4-5: TX Acknowledge Register
Direction
Output Transmits data to PHY
Output Transmits data enable to PHY
Output Transmits error signal to PHY
Input Recovered transmit clock by PHY
Input Carrier sense control signal from PHY
Input Collision detect control signal from PHY
Input Recovered clock from data stream by PHY
Input Receive data from PHY
Input Receive data valid control signal from PHY
Input Receive data error signal from PHY
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ACK seen here
D1
Ethernet MAC expects it to be held until here
Table 4-1 describes the MII interface signals.
Description
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
R
D2 D3
D1 D2
UG074_3_70_010906