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Chapter 4: Physical Interface
times of the input RGMII receiver signals which are sampled at the RGMII IOB input flip-
flops.
When operating at 10 Mb/s and 100 Mb/s, the DCM is bypassed and held in reset. This is
achieved using the BUFGMUX global clock multiplexer shown in
requirement to bypass the DCM because the clock frequency of RGMII_RXC_# is 2.5 MHz
when operating at 10 Mb/s and 2.5 MHz is below the DCM low frequency threshold for
Virtex-4 FPGAs. However, at the 10 Mb/s and 100 Mb/s operating speeds, input setup
and hold margins increase appropriately and the input RGMII data can be sampled
correctly without use of the DCM.
In the transmit path, the IDELAY provides a maximum shift of 4.7 ns. If this delay is not
sufficient to give the correct skew, the method shown in
ODDR is used to control the polarity of the RGMII_IOB_# signal that is fed to the IDELAY.
At 1 Gb/s, if the skew given by connecting the D1 and D2 inputs of ODDR to V
GND, respectively, is not sufficient, the D1 and D2 inputs can be inverted to yield a 4 ns
shift on the clock with respect to the data. As in
provide the correct skew.
The inversion must be removed from the EMAC#CLIENTTXGMIIMIICLKOUT signal for
correct operation at speeds below 1 Gb/s. The CLIENTEMAC#DCMLOCKED port must
be tied High.
Tri-Mode RGMII v1.3
Figure 4-16
specification v1.3. GTX_CLK must be provided to the Ethernet MAC with a high-quality
125 MHz clock that satisfies the IEEE Std 802.3-2002 requirements. The
EMAC#CLIENTTXGMIIMIICLKOUT port generates the appropriate frequency deriving
from GTX_CLK and depending on the operating frequency of the link. It clocks directly to
the RGMII_TXD_# ODDR registers.
The EMAC#CLIENTTXCLIENTCLKOUT output port connects to the
CLIENTEMAC#TXCLIENTCLKIN input port and transmitter client logic in the FPGA
fabric through a BUFG. The receiver client clocking is similar.
The RGMII_RXC_# is generated from the PHY and is connected to the PHYEMAC#RXCLK
pin and receive logic through a DCM and a BUFG. A DCM must be used on the
RGMII_RXC_# clock path as illustrated in
1 ns hold requirements at 1 Gb/s. Phase shifting may then be applied to the DCM to fine
tune the setup and hold times of the input RGMII receiver signals which are sampled at the
RGMII IOB input flip-flops.
When operating at 10 Mb/s and 100 Mb/s, the DCM is bypassed and held in reset. This is
achieved using the BUFGMUX global clock multiplexer shown in
requirement to bypass the DCM because the clock frequency of RGMII_RXC_# is 2.5 MHz
when operating at 10 Mb/s and 2.5 MHz is below the DCM low frequency threshold for
Virtex-4 FPGAs. However, at the 10 Mb/s and 100 Mb/s operating speeds, input setup
and hold margins increase appropriately and the input RGMII data can be sampled
correctly without use of the DCM. The CLIENTEMAC#DCMLOCKED port must be tied
High.
www.BDTIC.com/XILINX
120
shows the tri-mode clock management following the Hewlett Packard RGMII
www.xilinx.com
Figure
Figure 4-15
Figure
4-14, the IDELAY value is used to
Figure 4-16
to meet the RGMII 1 ns setup and
Figure
Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
R
4-14. It is a
can be used. Here an
and
CC
4-16. It is a
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