System Memory Design Guidelines (Ddr-Sdram) For So-Dimm Configuration; Table 20. Gmch Chipset Memory Signal Groups - Intel 855GM Design Manual

System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration

6. System Memory Design Guidelines
(DDR-SDRAM) for SO-DIMM
configuration
The Intel 855GM/GME chipset GMCH Double Data Rate (DDR) SDRAM system memory interface
consists of SSTL-2 compatible signals. These SSTL-2 compatible signals have been divided into several
signal groups: Data, Control, Command, CPC, Clock, and Feedback signals. Table 20 summarizes the
different signal grouping. Refer to the Intel
External Design Specification for details on the signals listed.

Table 20. GMCH Chipset Memory Signal Groups

Group
Clocks
Data
Control
Command
CPC
Feedback
76
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Signal Name Description
SCK[5:0] DDR-SDRAM Differential Clocks - (3 per SO-DIMM)
SCK#[5:0] DDR-SDRAM Inverted Differential Clocks - (3 per SO-DIMM)
SDQ[63:0] Data Bus
SDQ[71:64] Check Bits for ECC Function
SDQS[8:0] Data Strobes
SDM[8:0] Data Mask
SCKE[3:0] Clock Enable - (One per Device Row)
SCS#[3:0] Chip Select - (One per Device Row)
SMA[12:6,3,0] Memory Address Bus
SBA[1:0] Bank Select
SRAS# Row Address Select
SCAS# Column Address Select
SWE# Write Enable
SMA[5,4,2,1] Command per Clock (SO-DIMM0)
SMAB[5,4,2,1] Command per Clock (SO-DIMM1)
RCVENOUT# Receive Enable Output (no external connection)
RCVENIN# Receive Enable Input (no external connection)
855GM/GME (Montara-GM/GM+) Chipset GMCH
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Intel 855GM/855GME Chipset Platform Design Guide
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